Semiconductor chip with passive element in a wiring region...

Details Semiconductor chip with passive element in a wiring region... Semiconductor chip with passive element in a wiring region...

2006-03-14

2006-03-14

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S692000, C257S773000, C257S531000, C257S532000

Reexamination Certificate

active

07012339

ABSTRACT:
When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut from the wafer. In a case where a chip size package is made, the chip region is cut from the wafer after forming the redistribution wiring and external terminals and so forth over the whole of the chip region. As a result, the design of the integrated circuit and part of the fabrication process thereof can be shared by a chip which is mounted in a chip size package and a chip which is mounted in another type of package.

REFERENCES:
patent: 6211576 (2001-04-01), Shimizu et al.
patent: 6228684 (2001-05-01), Maruyama
patent: 6391685 (2002-05-01), Hikita et al.
patent: 6433422 (2002-08-01), Yamasaki
patent: 2002/0017730 (2002-02-01), Tahara et al.
patent: 2002/0149086 (2002-10-01), Aoki
patent: 2003/0189251 (2003-10-01), Terui et al.
patent: 9-64049 (1997-03-01), None
patent: 2000-243900 (2000-09-01), None
patent: 2000-299406 (2000-10-01), None

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