Semiconductor chip with bond area

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S700000, C257S759000, C257S774000, C438S011000, C438S623000, C438S637000

Reexamination Certificate

active

07947978

ABSTRACT:
A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

REFERENCES:
patent: 4051508 (1977-09-01), Sato
patent: 4685998 (1987-08-01), Quinn
patent: 5083187 (1992-01-01), Lamson
patent: 5226232 (1993-07-01), Boyd
patent: 5384488 (1995-01-01), Golshan
patent: 5468984 (1995-11-01), Efland
patent: 5506499 (1996-04-01), Puar
patent: 5532512 (1996-07-01), Fillion
patent: 5646439 (1997-07-01), Kitayama
patent: 5659201 (1997-08-01), Wollesen
patent: 5691248 (1997-11-01), Cronin
patent: 5792594 (1998-08-01), Brown
patent: 5834844 (1998-11-01), Akagawa
patent: 5854513 (1998-12-01), Kim
patent: 5883435 (1999-03-01), Geffken
patent: 5969424 (1999-10-01), Matsuki
patent: 6022792 (2000-02-01), Ishii
patent: 6066877 (2000-05-01), Williams
patent: 6077726 (2000-06-01), Mistry
patent: 6144100 (2000-11-01), Shen
patent: 6184143 (2001-02-01), Ohashi
patent: 6187680 (2001-02-01), Costrini
patent: 6229221 (2001-05-01), Kloen
patent: 6300234 (2001-10-01), Flynn
patent: 6359328 (2002-03-01), Dubin
patent: 6362087 (2002-03-01), Wang
patent: 6410435 (2002-06-01), Ryan
patent: 6429120 (2002-08-01), Ahn
patent: 6472745 (2002-10-01), Iizuka
patent: 6511901 (2003-06-01), Lam
patent: 6590295 (2003-07-01), Liao
patent: 6593222 (2003-07-01), Smoak
patent: 6614091 (2003-09-01), Downey
patent: 6639299 (2003-10-01), Aoki
patent: 6646347 (2003-11-01), Mercado
patent: 6683380 (2004-01-01), Efland
patent: 6707124 (2004-03-01), Wachtler
patent: 6780748 (2004-08-01), Yamaguchi
patent: 6798050 (2004-09-01), Homma
patent: 6800555 (2004-10-01), Test
patent: 6844631 (2005-01-01), Yong et al.
patent: 6864562 (2005-03-01), Toyosawa
patent: 6943440 (2005-09-01), Kim
patent: 6963136 (2005-11-01), Shinozaki
patent: 6979647 (2005-12-01), Bojkov
patent: 7239028 (2007-07-01), Anzai
patent: 7319277 (2008-01-01), Lin
patent: 7394161 (2008-07-01), Kuo
patent: 2001/0035452 (2001-11-01), Test
patent: 2001/0051426 (2001-12-01), Pozder
patent: 2002/0000671 (2002-01-01), Zuniga
patent: 2002/0043723 (2002-04-01), Shimizu
patent: 2002/0158334 (2002-10-01), Vu
patent: 2003/0197289 (2003-10-01), Lin
patent: 2003/0218246 (2003-11-01), Abe
patent: 2004/0023450 (2004-02-01), Katagiri
patent: 2004/0036170 (2004-02-01), Lee
patent: 2005/0121804 (2005-06-01), Kuo et al.
patent: 2006/0027933 (2006-02-01), Chen et al.
patent: 2008/0012132 (2008-01-01), Lin
patent: 2008/0206979 (2008-08-01), Fogel et al.
patent: 2008/0251924 (2008-10-01), Lin et al.
patent: 2009/0108453 (2009-04-01), Lin et al.
patent: 489346 (2002-06-01), None
patent: 1225288 (2004-12-01), None
Foreign Office Action and Search Report for Taiwan Patent Application No. 095145100 dated Jun. 29, 2010 with English Translated Summary.
Mistry, K. et al. “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeo, T-S. “ESD Effects On Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al., “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590.
Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-66.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) pp. 23-28.
Ingerly, D. et al. “Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing,” International Interconnect Technology Conference (2008) pp. 216-218.
Kurd, N. et al. “Next Generation Intel® Micro-architecture (Nehalem) Clocking.Architecture,” Symposium on VLSI Circuits Digest of Technical Papers (2008) pp. 62-63.
Maloney, T. et al. “Novel Clamp Circuits for IC Power Supply Protection,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C, vol. 19, No. 3 (Jul. 1996) pp. 150-161.
Geffken, R. M. “An Overview of Polyimide Use in Integrated Circuits and Packaging,” Proceedings of the Third International Symposium on Ultra Large Scale Integration Science and Technology (1991) pp. 667-677.
Luther, B. et al. “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices,” Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference (1993) pp. 15-21.
Master, R. et al. “Ceramic Mini-Ball Grid Array Package for High Speed Device,” Proceedings from the 45th Electronic Components and Technology Conference (1995) pp. 46-50
Maloney, T. et al. “Stacked PMOS Clamps for High Voltage Power Supply Protection,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings (1999) pp. 70-77.
Lin, M.S. et al. “A New System-on-a-Chip (SOC) Technology—High Q Post Passivation Inductors,” Proceedings form the 53rd Electronic Components and Technology Conference (May 30,

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor chip with bond area does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor chip with bond area, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip with bond area will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2677486

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.