Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-29
2004-12-28
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000, C257S507000, C257S510000
Reexamination Certificate
active
06835981
ABSTRACT:
This patent application is based upon and claims the benefit of the earlier filing date of Japanese Patent Application No. 2001-298533 filed Sep. 27, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor chip having a functional block positioned in an SOI (silicon-on-insulator) region and another functional block positioned in a bulk region in a single chip and a method for fabricating such a semiconductor chip.
2. Description of Related Art
DRAM chips having a 1T1C (1-transistor-1-capacitor) memory cell structure have been widely used as an inexpensive and large-capacity memory suitable for high-density integrated circuits. In recent years, demand has been increasing for a system LSI, in which a DRAM and a logic core are integrated in a single chip in order to improve system performance.
On the other hand, SOI devices, such as a SOIMOSFET, using an SOI substrate in place of a conventional silicon bulk substrate has been attracting a great deal of attention. In SOI devices, transistors are formed in the silicon layer positioned on the buried oxide (referred to as “SOI layer”) in an SOI substrate. Such SOI devices have already been mass-produced for use in high-performance logic circuits. Along with this trend, in order to further bring out the advantages of a high-performance logic circuit consisting of SOI devices (hereinafter referred to as an “SOI logic”), development of a system LSI or a system-on-chip which carries a memory (e.g., a DRAM) together with an SOI logic on a single chip has become an urgent necessity.
However, it is difficult to form a DRAM in an SOI substrate, employing the same structure with the high-performance logic devices (e.g., SOIMOSFETs), for several reasons.
First, leakage current or fluctuation of the threshold voltage will occur during operation because electric potential of the substrate (i.e., the body region) of the SOIMOSFET is floating. If such an SOIMOSFET is used as a path-transistor, leakage current (e.g., a parasitic MOSFET current or a parasitic bipolar-current) occurs depending on the operational conditions of the source/drain voltage, even if the gate voltage is in the OFF condition. For this reason, from a viewpoint of retention, the SOIMOSFET structure is unsuitable for DRAM cell transistors having a strict leakage-current spec.
Second, the threshold voltage varies in accordance with changes in the operational conditions, including operation hysteresis, due to the floating body effect. Accordingly, if the sense amplifier of the DRAM is comprised of SOIMOSFETs, variation in the threshold voltage between the pair transistors is amplified, and the sense margin deteriorates.
To solve the problem of the floating body effect, a technique for fixing the body potential by providing a contact to the additional device region extracted from the body of the conventional MOSFET pattern was proposed. However, this method increases the occupied area of both the memory cell and the sense amplifier greatly, and spoils the high integration feature, which is the main characteristic of a DRAM.
Then it is proposed to form a bulk substrate region as a portion of an SOI substrate, and to form circuits, such as DRAMs, which are incompatible with the floating body effect, in the bulk substrate region. In fact, various methods for fabricating a substrate having both a bulk structure and an SOI structure (referred to as an “SOI/bulk substrate”) have been proposed.
A first approach is a SIMOX (separation by implanted oxygen) technique using a mask pattern (Japanese Patent Application Laid-open (Kokai) No 10-303385, and Robert Hannon, et al. 2000 Symposium on VLSI Technology of Technical Papers, p66-67). With this method, oxygen is implanted in predetermined positions in the silicon bulk substrate to produce an SOI structure that coexists with the silicon bulk region.
A second approach is a wafer bonding technique for bonding a silicon substrate onto another silicon substrate with a patterned insulator (Japanese Patent Application Laid-open (Kokai) No. 8-316431).
A third approach is to etch the SOI layer and the buried oxide at a predetermined position of the SOI substrate to partially expose the base substrate, thereby producing a bulk region in the SOI substrate (Japanese Patent Application Laid-open (Kokai) Nos. 7-106434, 11-238860, and 2000-91534).
A fourth approach is to form all epitaxially grown silicon layer on the base substrate in order to eliminate the level difference between the SOI substrate region and the bulk region resulting from the partial etching in the third approach (Japanese Patent Application Laid-open (Kokai) No. 2000-243944). In this method the epitaxial layer is grown until it exceeds the mask layer placed over the SOI substrate region, and then it is planarized using the mask layer as a stopper.
There are problems with these approaches to forming an SOI/bulk substrate.
The first approach deteriorates the crystalline characteristic of the SOI layer due to the implantation of oxygen ions. In addition, volume expansion that occurs when the buried oxide is formed by reaction between silicon and the implanted oxygen in a thermal process causes stress, and crystal defect is produced at the boundary between the SOI substrate region and the bulk region.
The second approach produces an undesirable interface state and a crystal-defect layer, which deteriorate both the crystal characteristic and the electrical characteristic at the bonding surface between the two substrates. Such an interface state and crystal defect are due to contamination and shifting of crystal orientation.
The third approach causes a level difference between the SOI substrate region and the bulk region by an amount corresponding to the thickness of the SOI layer and the buried oxide. This level difference makes it difficult to guarantee the focusing margin in the photolithography process, and to control the height of the buried insulator in the trench when forming isolations.
In the fourth approach, the crystal line characteristic of the epitaxial growth layer may deteriorate near the interface between the bulk region and the SOI substrate region. This problem is caused by the fact that crystal grows from both the top face of the base substrate and the sidewall of the SOI layer during the formation of the bulk growth layer. The crystal characteristic of the epitaxial layer having grown from the etched side face of the SOI substrate is inherently bad. In addition, the crystal orientations of the epitaxial layers having grown from the top surface of the base substrate and from the sidewalls of the SOI layer are mismatched with each other at the interface between them further deteriorating the crystal characteristic.
Then, it is conceived to cover the exposed sidewall of the SOI layer with a protection film, such as silicon nitride film, before forming the epitaxial growth layer in order to solve the above-described problem.
However, if a sidewall protection film (e.g., Si
3
N
4
) exists at the boundary between the epitaxially grown bulk region and the SOI substrate region, a relatively large stress is produced in both the epitaxial growth layer and the SOI layer over several micrometers near the boundary, depending on the process conditions. Such stress may cause change in the mobility of the carriers and crystal defect. If a transistor is positioned in an area having crystal defect, the device characteristic becomes inferior.
Furthermore, because the epitaxial growth layer is polished using the mask layer as a stopper, the final level of the epitaxial growth layer close to the boundary in the bulk region becomes higher than the SOI layer of the SOI substrate region equivalent to the thickness of the mask layer. To avoid the surface unevenness, a troublesome after-treatment, for example, re-polishing the epitaxial growth layer after thinning the mask layer, must be carried out. If the epitaxial growth layer is set broad in order to form a DRAM macro in it, dishi
Mizushima Ichiro
Nagano Hajime
Nitta Shinichi
Oyamatsu Hisato
Sato Tsutomu
Dickey Thomas L
Tran Minhloan
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