Semiconductor chip stack-type package and method of...

Details Semiconductor chip stack-type package and method of... Semiconductor chip stack-type package and method of...

2008-08-21

2010-12-07

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S686000, C257S777000, C257SE23040

Reexamination Certificate

active

07847396

ABSTRACT:
Embodiments of the inventive concept provide a semiconductor chip stack-type package. The package comprises a lead frame including a die paddle part and a lead part, a first semiconductor chip group and a second semiconductor chip group stacked sequentially and mounted on one surface of the die paddle part, a first wiring board between the first semiconductor chip group and the second semiconductor chip group, and second semiconductor chip group bonding wires for electrically connecting the second semiconductor chip group to the first wiring board. End portions of the first wiring board are electrically connected to inner leads of the lead part, which is adjacent to the die paddle part.

REFERENCES:
patent: 6690089 (2004-02-01), Uchida
patent: 2002/0130399 (2002-09-01), Moon
patent: 2006/0175715 (2006-08-01), Hirose et al.
patent: 2003-332521 (2003-11-01), None
patent: 2006-216911 (2006-08-01), None
patent: 1999-0060952 (1999-07-01), None
patent: 10-2006-0090173 (2006-08-01), None

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