Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-07-20
2003-06-17
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S786000
Reexamination Certificate
active
06580092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip, a semiconductor device on which a semiconductor chip is mounted, and a process for producing a semiconductor device, and more specifically to a semiconductor chip, such as a DRAM, an SRAM, a flash memory, a central processing unit (CPU), a micro-processing unit (MPU) or a digital system processor (DSP), having a terminal for making a test thereof easy, a semiconductor device on which such a semiconductor chip is mounted, and a process for producing such a semiconductor device.
2. Description of the Background Art
In many cases, a system composed of a combination of a memory such as a DRAM, an SRAM or a flash memory with a CPU, an MPU or a DSP is produced and used as one system unit.
FIG. 10
is a view illustrating an example produced at the earliest times when such a system semiconductor device was distributed. A memory semiconductor chip
110
is connected to a CPU
111
and a DSP
112
, which are logic semiconductor chips, through its leads
125
and substrate wiring
119
, and they are mounted on a single wiring substrate
107
. Distribution of such a system semiconductor device made it possible to select and use a desired system without requiring many steps for design of the system and so on. A drawback of this system semiconductor device is that its size becomes large so that it is unsuitable for use in a portable terminal or the like device.
FIG. 11
is a view illustrating a one-chip consolidation semiconductor device wherein plural semiconductor circuits are consolidated on a plane to make its size small. This device is a device suggested to overcome the above-mentioned problem. In this semiconductor device, respective semiconductor blocks are integrated with each other and formed on a single semiconductor substrate. Specifically, in this one-chip consolidation semiconductor device, a memory semiconductor block
110
and a logic semiconductor block
111
are simultaneously made on a semiconductor substrate
101
in the same processing step. For this reason, semiconductor circuits having different purposes are formed on respective areas in the single semiconductor substrate. The respective semiconductor circuit blocks are connected to each other through metal wires
119
made at the same time when the semiconductor circuit blocks themselves were made. In this one-chip consolidation semiconductor device, test terminals (testing terminal)
103
that are to be connected to a tester and circuit-constituting terminals
105
that are to be connected to terminals of any other element are separately connected to wires for terminals that are extended from the respective semiconductor chips themselves, and constitute rows. It has been promoted that system semiconductor devices are made small and thin, using such a one-chip consolidation semiconductor device.
However, the above-mentioned one-chip consolidation semiconductor device has the following problem. A memory semiconductor circuit such as a DRAM has a much complicated structure and it must be produced through a very troublesome process for forming memory cells. On the other hand, a logic circuit such as a CPU has a simple structure so that the process for producing the same is also relatively simple. In the case that logic circuits are produced on a semiconductor substrate in a one-chip consolidation semiconductor device at the same time when memories are produced, blocks of the logic circuits are subjected to useless heat treatment and so on for a long time so that the performance of the system may become bad. This causes a problem that by adopting one-chip consolidation, the date of delivery of the semiconductor devices is delayed and the entire structure of the memories and the logic circuits becomes complicated so that the yield of the devices drops. Therefore, difficulty becomes larger about one-chip consolidation semiconductor devices as the devices are becoming more minute so that the capacity of their memories becomes larger.
To overcome this problem, stack-type consolidation chips as shown in
FIGS. 12A and 12B
are suggested (Japanese Patent Laying-Open No. 2000-114452 (2000), Japanese Patent Laying-Open No. 11-214448 (1999) and so on).
FIG. 12A
is a sectional view of a semiconductor device wherein semiconductor chips are stacked and mounted, and
FIG. 12B
is a plan view of each semiconductor chip in the semiconductor device. In
FIG. 12A
, respective stacked chips
110
a
and
110
b
are beforehand produced and their performance is tested before the chips are stacked. Thus, it is checked whether the chips get through the test or not. In a packaging step, the following is merely performed: terminals
105
a
and
105
b
of the semiconductor chips mounted on a die pad
106
are connected through a wire
109
and the terminal
105
b
and a lead terminal
106
a
are connected through another wire
109
. Therefore, the logic semiconductor chip is not subjected to any long-sustained heat treatment required for producing memories, so that a high yield can be kept in the production of large-scale integrated system semiconductor devices. As illustrated in
FIG. 12B
, all of the terminals of the semiconductor chips constituting a package are composed of circuit-constituting terminals
105
. The semiconductor chips are tested using the circuit-constituting terminals.
However, in the semiconductor chips having only the circuit-constituting terminals shown in
FIG. 12B
, the circuit-constituting terminals also function as test terminals. Thus, it may be impossible that appropriate wiring for terminals is led out from a site necessary for the test and then the test is performed. Specifically, no terminals may be set up at sites where an examiner wants to obtain testing signals actually since the real terminals are set up mainly to constitute circuits. For a thoroughgoing test, it is necessary that respective terminals of the individual terminal output an intense signal to a test device. For this, it is necessary that a driver etc. for outputting such an intense signal are fitted up to each of the semiconductor chips. If such a driver is fitted up, problems as follows arise: parasitic capacitance is generated; the structure of the circuits becomes still more complicated; and electric current consumption increases. In circuit-design and actual production of consolidated semiconductor chips, it is a heavy load to add such drivers and the like elements. It is therefore desired to avoid the fitting-up of the driver in each of the chip circuits. However, if a driver as described above is not fitted up to a certain semiconductor chip, the output signal is weak. As a result, for example, the semiconductor chip cannot be tested at a high speed. Needless to say, it is desired that the performance of semiconductor chips having a minute and complicated circuit is checked in a thoroughgoing test and then the chips are forwarded.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor chip that can easily be subjected to a thoroughgoing test without imposing a burden on its circuit; a semiconductor device on which such a semiconductor chip is mounted; and a process for producing such a semiconductor device.
The semiconductor chip of the present invention includes a first test terminal connected to a terminal line that extends from a body of the chip, the first test terminal being a terminal for being jointed to a test device; and a circuit-constituting terminal branched from the terminal line and connected to the terminal line, the circuit-constituting terminal being a terminal for being connected to any other circuit element.
Since the circuit-constituting terminal and the first test terminal are terminals different from each other, this structure makes it possible to arrange the two terminals at a position convenient for the structure of the circuit and at a position convenient for a test, respectively. The above-mentioned other circuit element may be a semiconductor chip or a circuit element th
Jackson Jerome
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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