Semiconductor chip package with multilevel leads

Details Semiconductor chip package with multilevel leads Semiconductor chip package with multilevel leads

2000-04-25

2002-04-23

Donovan, Lincoln (Department: 2832)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S692000, C257S787000

Reexamination Certificate

active

06376903

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor chip package with multilevel leads, and more particularly, to a semiconductor chip package which can minimize the chip package size and reduce the resistance of the leads.
DESCRIPTION OF THE BACKGROUND ART
In view of the use of large scale integration, large storage capacity, high speed and the multi-function of semiconductor memory devices in recent years, a semiconductor chip package for these devices has become larger due to the increasing number of input/output pins. Chip packages have become a perfect square due to the increased memory storage capacity, the high speed capacity of semiconductor memory elements, and the increased number of input/output pins for data.
Accordingly, U.S. Pat. Nos. 4,862,245 and 5,535,509 disclose lead-on-chip (LOC) packages for reducing a chip size of a semiconductor memory chip package. However, size reduction is limited because the leads must have at least a certain width and interval in a LOC package.
As shown in
FIG. 1
, a conventional semiconductor chip package is constructed with a molded material such as plastic or resin epoxy, encapsulating a semiconductor chip
10
, bonding wires
14
, inner leads
16
, while outer leads
18
are exposed from the molded housing
20
. Contact pads
12
of the semiconductor chip are electrically coupled to the inner leads
16
via the bonding wires
14
. The exposed outer leads
18
are electrically connected to conductive lines of a printed circuit board (not shown).
For minimizing the resistance and coupling resistance, the outer leads
18
have a larger width relative to the inner leads
16
. The length of a longer side of the package is determined according to that of a longer side of a lead frame, independent of a chip itself, since the leads are arranged in a certain interval.
Accordingly, it is desirable to reduce the length of a longer side of the lead frame for minimizing the package size in a LOC package.
U.S. Pat. No. 4,801,765 discloses the structure having multilevel lead frames, in which inner leads on an upper frame are interdigitated with those of a lower frame in a quad package and outer leads of the upper frame are coplanar with outer leads of the lower frame. The package size is not reduced in this structure.
U.S. patent appln. Ser. No. 60/032,575 filed on Dec. 4, 1996 discloses a multilevel lead frame having signal leads and conductive sides in a quad package. However, certain leads to which a power supply voltage and a ground voltage are applied are formed as conductive sides, and a plurality of signal leads are disposed above the conductive sides. Accordingly, the plurality of signal leads are arranged at a certain interval and width on the same plane so that it is difficult to provide a small chip package.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor chip package is provided with multilevel leads which minimizes the package size by laminating leads to form multilevel leads. This reduces the resistive components and coupling resistance of leads by providing increased width of leads.
To accomplish the foregoing, a semiconductor chip package according to the present invention is provided which comprises a semiconductor chip having a plurality of contact pads.
The package includes a plurality of first leads each including an inner lead portion which is electrically coupled to an associated contact pad on the semiconductor chip, and an outer lead portion which extends from the inner lead portion and is exposed outside the package. A plurality of second leads are disposed overlapping the plurality of first leads and are electrically insulated from the first plurality of leads. Each lead of the second plurality of leads includes an inner lead portion electrically coupled to an associated contact pad on the semiconductor chip and an outer lead portion which extends from the inner lead portion and is exposed outside the package. A molded housing encapsulates the semiconductor chip and the inner lead portions of the first and second plurality of leads.
Each outer lead portion of the first leads is bent downward at 90 degrees, and then bent toward the housing at 90 degrees. Preferably, each outer lead portion of the second leads is bent downward at 90 degrees, and then bent away from the housing at 90 degrees. Also, the first leads are formed in a lower lead frame, and the second leads are formed in an upper lead frame. The inner ends of the first leads are longer than the inner ends of the second leads by an amount sufficient to provide an area for wire bonding to the first leads.
According to another aspect of the present invention, a device includes a semiconductor chip; a plurality of first and second leads; and a housing. The semiconductor chip includes a plurality of contact pads. The plurality of first and second leads each include inner lead portions and outer lead portions. The inner lead portions of each of the first and second leads are electrically coupled to an associated contact pad, and disposed overlapping and insulated from each other. The outer lead portions of the first and second leads, which are exposed outside, are reciprocally disposed at the same plane. The housing encapsulates the semiconductor chip and the inner lead portions of the plurality of first and second leads.
According to still another aspect of the present invention, a device includes a semiconductor chip, a plurality of first leads, a plurality of second leads and a housing. The plurality of first leads each include inner lead portions and outer lead portions. The inner lead portions are electrically coupled to associated contact pads on the semiconductor chip, and include straight portions and oblique portions which extend from the straight portions at a predetermined angle. The outer lead portions extend from the oblique portions of the inner lead portions and are bent in a first direction.
The plurality of second leads each include an inner lead portion, an outer lead portion and an oblique portion. The inner lead portions of the second leads are disposed overlapping the straight inner lead portions of the first leads and are electrically insulated from the first leads. The inner lead portions of the second leads are electrically coupled to associated contact pads on the semiconductor chip. The oblique portions extend from the inner lead portions at a predetermined angle. The terminating ends of the outer lead portions are coplanar with the terminating ends of the outer lead portions of the first leads. The housing encapsulates the semiconductor chip and the inner lead portions and the oblique portions of the plurality of first and seconds leads.


REFERENCES:
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patent: 4862245 (1989-08-01), Pashby et al.
patent: 5287000 (1994-02-01), Takahashi et al.
patent: 5535509 (1996-07-01), Tomita et al.
patent: 5554886 (1996-09-01), Song
patent: 5744827 (1998-04-01), Jeong et al.
patent: 5819403 (1998-10-01), Crane, Jr. et al.
patent: 5909053 (1999-06-01), Fukase et al.
patent: 6016003 (2000-01-01), Uemura
patent: 6080931 (2000-06-01), Park et al.

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