Semiconductor chip package structure

Details Semiconductor chip package structure Semiconductor chip package structure

1999-04-05

2000-06-27

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

257788, H01L 2348, H01L 2352, H01L 2940

Patent

active

060810386

ABSTRACT:
The object of the present invention is to provide a semiconductor chip package structure in which thermal stress exerted on a wiring substrate is mitigated to improve the reliability of the bond between the semiconductor chip and the wiring substrate and the bond between the wiring substrate and the motherboard.
To achieve the above object, the present invention provides a semiconductor chip package structure in which a semiconductor chip is mounted on a wiring substrate by flip chip bonding to a wiring pattern on the wiring substrate, comprising: a large number of electrode terminals disposed on an electrode arrangement surface of the semiconductor chip; a first group of the electrode terminals electrically connected to the wiring pattern by an adhesive layer; and a second group of the electrode terminals electrically connected to the wiring pattern by an elastomer layer.

REFERENCES:
patent: 5834848 (1998-11-01), Iwasaki
patent: 5959362 (1999-09-01), Yoshino

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