Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2001-10-09
2003-08-19
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S678000, C257S720000
Reexamination Certificate
active
06608380
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2000-59189, filed on Oct. 9, 2000, the contents of which are herein incorporated by reference in their entirety
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices and, more particularly, to a semiconductor chip package and a method for manufacturing the same.
2. Description of the Related Art
Usually, wire bonding is used for making electrical connections between central processing unit (CPU) chips and semiconductor packages. Recently, in order to meet a pressing demand for increased speed, a flip-chip bonding method has been employed. The structure of semiconductor packages using the flip-chip bonding method can be divided into two types, i.e. a lid type and a non-lid type. The lid type is applied in a semiconductor chip package comprising a high-frequency CPU chip with high heating value, and the non-lid type is applied in a semiconductor chip package comprising a low-frequency CPU chip with low heating value.
FIG.
1
and
FIG. 2
show a conventional semiconductor chip package
100
having a lid
40
. A CPU chip
20
is attached to the upper surface of a ceramic substrate
10
using the flip-chip bonding method and covered with a lid
40
. Pluralities of external connection pins
60
, which are electrically connected to the CPU chip
20
, extend from a lower surface of the ceramic substrate
10
. A flip chip bonding part between the CPU chip
20
and the ceramic substrate
10
is filled with an epoxy resin using an under-filling method. Notches
44
are formed through the lid
40
and spaced at a predetermined distance. A screw
42
is close fit on each notch
44
and combines with a heat sink (not shown) for the package
100
.
The lid
40
is made of a material having a good heat emissive capacity such as Al or Cu, and comprises a cavity
48
for receiving the CPU chip
20
and the capacitors
30
on its lower surface. In order to maximize the heat emissive capacity through the lid
40
, a thermal interface material
56
is interposed between a bottom surface of the cavity
48
of the lid
40
and an upper surface of the CPU chip
20
. Thermosetting silicon adhesive is used as a sealant
54
for attaching the lid
40
to the upper surface of the ceramic substrate
10
. After applying the sealant
54
to the perimeter of the ceramic substrate
10
, the lid
40
is attached and the sealant
54
is hardened.
Thus, the cavity
48
is hermetically sealed. If the sealant
54
is hardened at a high temperature, the gas emitted by hardening the sealant
54
and air within the cavity
48
are expanded and then leaked through the sealant
54
, thereby causing voids or cracks in the sealant
54
.
Such a package is detected as a failure in the reliability test, i.e. Pressure Cooker Test (PCT). Voids or cracks in the sealant
54
are routes for penetrating the cavity
48
in the lid
40
with moisture. Herein, PCT is a moisture-resistant test carried out in a pressure cooker of 29.4 psi pressure, 100% humidity, and 121±2° C. temperature.
FIG. 3
shows another conventional semiconductor chip package
200
having a lid
140
with a venting hole
146
. Referring to
FIG. 3
, the foregoing problem is prevented by forming the venting hole
146
on the lid
140
. However, this package
200
also has some drawbacks in that the venting hole
146
should also be hermetically sealed. Further, if a thermosetting sealant
158
is used, which is the same material as the sealant
154
, voids also occur in the sealant
158
.
If a sealant which can be hardened at room temperature is used, failures due to air expansion, i.e. voids or cracks are prevented; the drawback being that the hardening time of this sealant, approximately 24 hours, is much longer than that of the other thermosetting sealant, about 1 hour, thereby decreasing productivity.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to hermetically seal the venting holes formed through the lid without creating any voids or cracks in the sealant.
The present invention contemplates, in general, a semiconductor chip package comprising a chip with a lid having venting holes hermetically sealed with screws and a manufacturing method thereof. The semiconductor chip package of the present invention comprises a chip; a substrate having upper and lower surfaces, the chip being attached to the upper surface of the substrate; external connection terminals extending from the lower surface of the substrate and electrically connected to the chip; a lid attached to the upper surface of the substrate. The lid includes a cavity for receiving the chip on a lower surface and also venting holes penetrating the lid. The package further includes sealing screws for hermetically sealing the venting holes.
At least one heat sink-attaching screw for being coupled to a heat sink is attached to an upper surface of the lid.
At least one hole for attaching the heat sink-attaching screw is formed on the upper surface of the substrate, and at least one of the holes penetrates the lid. Herein, the hole penetrating the lid is a venting hole, and the sealing screws can be the heat sink-attaching screws.
Further, a rubber packing is formed on the sealing screw on the upper surface of the lid.
The method for manufacturing semiconductor chip packages of the present invention comprises (a) preparing a substrate, the substrate having upper and lower surfaces, and a plurality of external connection pins extending from the lower surface; (b) attaching a chip to the upper surface of the substrate; (c) attaching a lid to the upper surface of the substrate, the lid comprising a cavity for receiving the chip on a lower surface and venting holes; and (d) hermetically sealing the venting holes with sealing screws.
REFERENCES:
patent: 4897508 (1990-01-01), Mahulikar et al.
patent: 5504372 (1996-04-01), Braden et al.
patent: 6294408 (2001-09-01), Edwards et al.
Chun Jung-Hwan
Kwon Heung-Kyu
Ro Young-Hoon
Andújar Leonardo
Flynn Nathan J.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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