Semiconductor chip package having decoupling capacitor and...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S728000, C257S691000, C257S698000, C257S707000, C257S710000, C257S700000, C257SE23001, C257SE23051, C257SE23069, C257SE23114, C257SE23144, C257S737000, C257S924000, C361S763000

Reexamination Certificate

active

07129571

ABSTRACT:
A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

REFERENCES:
patent: 5796170 (1998-08-01), Marcantonio
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6020637 (2000-02-01), Karnezos
patent: 6118178 (2000-09-01), Takeuchi
patent: 6222246 (2001-04-01), Mak et al.
patent: 6307255 (2001-10-01), Stave
patent: 6407929 (2002-06-01), Hale et al.
patent: 6445594 (2002-09-01), Nakagawa et al.
patent: 6538313 (2003-03-01), Smith
patent: 6717248 (2004-04-01), Shin et al.
patent: 6833614 (2004-12-01), Higuchi
patent: 6936922 (2005-08-01), Park et al.
patent: 05-166876 (1993-07-01), None
patent: 05-291347 (1993-11-01), None
English language abstract of the Japanese Publication No. 05-166876.
English language abstract of the Japanese Publication No. 05-291347.

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