Semiconductor chip package and method of fabricating same

Details Semiconductor chip package and method of fabricating same Semiconductor chip package and method of fabricating same

1999-10-12

2002-10-01

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000, C438S121000, C438S124000

Reexamination Certificate

active

06458627

ABSTRACT:

This application claims the benefit of Application No. 18251/2999, filed in Korea on May 20, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to a semiconductor chip package and a method of fabricating a semiconductor chip package that reduces chip size package (CSP).
2. Description of the Related Art
There is an increasing demand for small-sized and lightweight electronic system units. In order to satisfy such demands, efforts have been made to reduce the size of semiconductor chips by decreasing circuit wire width and by reducing semiconductor chip package size. The structure and fabrication method of a conventional semiconductor chip package will now be explained with reference to
FIGS. 1A
to
1
E.
As illustrated in
FIG. 1E
, a semiconductor chip
12
adheres to an upper center portion of a substrate
10
of a semiconductor chip package by an adhesive
13
. One side edge of a multi-layer wiring
11
, which is formed on the substrate
10
, is connected to a pad (not shown) on the semiconductor chip
12
by a wire
14
. A liquid sealing material
17
having a high viscosity surrounds the semiconductor chip
12
, the wire
14
and the one side edge of the multi-layer wiring
11
. A solder resist
18
covers an upper portion of the other side edge of the multi-layer wiring
11
, and a solder ball
19
is mounted on a predetermined portion thereof.
The fabrication method of the conventional semiconductor chip package as shown in
FIG. 1E
will now be explained.
First, as shown in
FIG. 1A
, the substrate
10
of the semiconductor chip package is prepared. The substrate
10
of the semiconductor chip package has a groove at its upper center portion. The multi-layer wiring
11
is formed on the substrate
10
outside the groove. The solder resist
18
covers the entire upper surface except for the one-side edge of the multi-layer wiring
11
. After the substrate
10
is thus prepared, the unit semiconductor chip
12
is separated (by sawing, for example) from a wafer and is mounted on the groove of the substrate
10
using the adhesive
13
.
As shown in
FIG. 1B
, the pad (not shown) on the upper surface of the semiconductor chip
12
is connected to the one side edge of the multi-layer wiring
11
by the wire
14
.
As shown in
FIG. 1C
, a dam
16
is formed with a liquid resin having a sufficiently high viscosity at a predetermined portion of the multi-layer wiring
11
using a dispenser
15
.
As shown in
FIG. 1D
, the semiconductor chip
12
, the wire
14
and one side edge of the multi-layer wiring
11
inside the dam
16
are sealed by the liquid sealing material
17
.
As shown in
FIG. 1E
, the solder resist
18
on the multi-layer wiring
11
is partially etched and removed, and a solder ball
19
is mounted thereon by a reflow process.
However, in the conventional package fabrication method, the substrate of the semiconductor package and the semiconductor chip are separately fabricated, and then the semiconductor chip is mounted on the substrate. As a result, the completed semiconductor chip package is thick and big. Thus, the semiconductor chip package does not provide small-sized and lightweight electronic systems. Also, the fabrication cost of the package also increases because the substrate for the semiconductor package is separately fabricated.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor chip package and fabrication method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor chip package having the same size as a semiconductor chip fabricated by spreading a thermosetting resin on a semiconductor chip and forming a printed circuit wiring thereon.
Another object of the present invention is to provide a fabrication method for a semiconductor chip package that improves productivity by simultaneously packaging a plurality of semiconductor chips.
Another object is to provide a fabrication method for a semiconductor chip package that is integral with a semiconductor chip.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor chip package comprises a semiconductor chip having an upper, a bottom, and side surfaces; a plurality of pads respectively disposed on portions of the upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface the semiconductor chip, the thermosetting resin defining through-holes to expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin and at least one of the multi-layer wiring pattern and the connecting unit such that at least one through-hole exposes a portion of at least one of the multi-layer wiring pattern and the connecting unit; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the at least one of the multi-wiring pattern and the connecting unit.
In another aspect, a method of fabricating a semiconductor chip package comprises the steps of preparing a wafer including a plurality of semiconductor chips having a plurality of pads on an upper surface of each semiconductor chip; spreading a thermosetting resin on the wafer; separating the respective plurality of semiconductor chips; providing a heat sink member including a metal ring frame having grooves at a side of the metal ring frame and a metal film disposed on a lower surface of the metal ring frame; mounting a wiring member chip on the heat sink member; mounting the semiconductor chip on the wiring member; the wiring member defining openings such that the pads are exposed; filling a polymer resin between the semiconductor chip and the metal film; forming a wiring pattern by patterning the wiring member; exposing the pads; forming a connection to electrically connect the pads to the wiring pattern; spreading a solder resist on the thermosetting resin and at least one of the wiring pattern and the connection; removing a portion of the solder resist to expose a portion of at least one of the wiring pattern and the connection; and mounting a solder ball on the exposed portion of the at least one of the writing pattern and the connection.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5723907 (1998-03-01), Akram
patent: 5777379 (1998-07-01), Karavakis et al.
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 6020220 (2000-02-01), Gilleo et al.

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