Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2000-06-26
2001-04-10
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S106000, C438S107000, C438S110000, C438S112000, C438S108000, C438S126000
Reexamination Certificate
active
06214648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip package and, more particularly, to a semiconductor chip package in which longitudinal and transverse direction package stacking is made easy for reducing mounting area and increasing integrated capacity per unit mounting area; and a method for fabricating the same.
2. Discussion of the Related Art
There are, in general, the hole insertion mounting type semiconductor chip package and the surface mounting type semiconductor chip package. In the hole insertion mounting type semiconductor chip package, outer leads of the package are inserted into holes formed in an interconnection substrate and then soldered. Typical hole insertion mounting type semiconductor chip packages include DIP (Dual Inline Package), SIP (Single Inline Package), PGA (Pin Grid Array), and etc. In the surface mounting type semiconductor chip package, the package is mounted on a surface of the interconnection substrate. Typical surface mounting type semiconductor chip packages include SOP (Small Outline Package), SOJ (Small Outline J-bend), QFP (Quad Flat Package), and etc.
Of the conventional semiconductor chip packages, the DIP, SOP and SOJ chip packages disadvantageously require a large mounting area (i.e., total connection area between the chip package and the interconnection substrate) because the outer leads thereof project from both sides of the package body and no stacking is possible. That is, a semiconductor chip package of the DIP, SOP and SOJ types has a limited overall device packing density, and the packing density cannot be increased unless a wider mounting board is used because all the leads projecting from both sides of the package body must come in contact with connection pads on the interconnection substrate. Moreover, because creating these conventional semiconductor chip packages requires many steps in the packaging process, such as trimming of dam bars supporting bars of the lead frame and bending the outer leads to a required form, many problems, such as a drop in productivity, exist.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor chip package and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor chip package and method of fabricating the same which increases the packing density per unit of mounting area.
These and other objects are achieved by providing a semiconductor chip package, comprising: a package body including a recess and a plurality of barrier parts formed along one side thereof, each of the barrier parts having a first region and a second region projecting from the first region, adjacent first regions being separated by a slot; a semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, disposed in the recess of the package body; a conductive member disposed in each slot; a connecting member, associated with each bonding pad, electrically connecting the associated bonding pad with a corresponding conductive member; and a sealing member sealing the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members.
These and other objectives are further achieved by providing a semiconductor chip package, comprising: at least first and second packages, each of said first and second packages including, a package body including a recess and a plurality of barrier parts formed along one side thereof, each of the barrier parts having a first region and a second region projecting from the first region, adjacent first regions being separated by a slot; a semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, disposed in the recess of the package body; a conductive member disposed in each slot adjacent to one of the second regions, each conductive member and adjacent second region forming a projecting member, and adjacent projecting members being separated by a gap; a connecting member, associated with each bonding pad, electrically connecting the associated bonding pad with a corresponding conductive member; a sealing member sealing the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members; and the projecting members of the first package interdigitating with the projecting members of the second package.
These and other objectives are still further achieved by providing a semiconductor chip package comprising: at least first and second packages, each of said first and second packages including, a package body including a recess and a plurality of barrier parts formed along one side thereof, each of the barrier parts having a first region and a second region projecting from the first region, adjacent first regions being separated by a slot; a semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, disposed in the recess of the package body; a conductive member disposed in each slot adjacent to one of the second regions; a connecting member, associated with each bonding pad, electrically connecting the associated bonding pad with a corresponding conductive member; a sealing member sealing the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members; and the second package being stacked on the first package with each conductive member of the second package being electrically connected to a corresponding one of the conductive members of the first package.
These and other objectives are also achieved by providing a method for fabricating a semiconductor chip package, comprising the steps of: (a) forming a package body with a plurality of conductive members attached thereto, the package body including a recess and a plurality of barrier parts formed along one side thereof, each of the barrier parts having a first region and a second region projecting from the first region, adjacent first regions being separated by a slot, and one of the conductive members disposed in each slot; (b) disposing a semiconductor chip in the recess of the package body, the semiconductor chip including a reference surface having a circuit and a plurality of bonding pads formed thereon; (c) electrically connecting each bonding pad with a corresponding conductive member; and (d) sealing the semiconductor chip and at least a portion of the conductive members in electrical contact with the semiconductor chip.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
REFERENCES:
patent: 3489956 (1970-01-01), Yani et al.
patent: 4672151 (1987-06-01), Yamamura
patent: 5377077 (1994-12-01), Burns
patent: 5574314 (1996-11-01), Okada et al.
Birch & Stewart Kolasch & Birch, LLP
Hyundai Electronics Industries Co,. Ltd.
Tsai Jey
Zarneke David A.
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