Semiconductor chip package and manufacturing method thereof

Details Semiconductor chip package and manufacturing method thereof Semiconductor chip package and manufacturing method thereof

1999-09-07

2002-02-19

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S692000, C257S695000, C257S670000, C257S784000, C257S787000, C257S668000, C257S666000, C257S671000, C257S676000

Reexamination Certificate

active

06348729

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to an electronic device, and more particularly to a semiconductor chip package and a manufacturing method thereof, wherein a semiconductor die is encapsulated by a plastic package body in a manner that the backside surface of the die is exposed through the plastic package body.
2. Description of the Related Art
FIG. 1
depicts a conventional semiconductor chip package including a lead frame for supporting a semiconductor die
100
. The lead frame includes a plurality of leads having outer lead portions
106
and inner ends
107
. The die
100
is attached onto a die pad
111
by means of a silver paste
114
. The die pad
111
is connected to the lead frame by supporting bars (not shown in FIG.
1
). The outer lead portions
106
are used for electrical coupling to an outside circuit. The die
100
has bonding pads
117
electrically interconnected to the inner ends
107
of the lead frame though bonding wires
115
. The die
100
, the die pad
111
, the inner ends
107
of the lead frame and bonding wires
115
are encapsulated in a plastic package body
116
made of insulating material such as epoxy.
Because the plastic package body
116
completely surrounds the die
100
, the heat generated from the die
100
during normal operation must pass through the package body
116
to outside. Due to the insulating properties of the package body
116
, heat dissipation from the die
100
is resisted, thereby creating, in some instances, high temperatures within the conventional package which might impair or damage the die
100
.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a semiconductor chip package comprising a lead frame having a window pad for the supply of ground potential and a die enclosed in a plastic package body, wherein the lower surface of the lead frame and the backside surface of the die are exposed through the plastic package body for improving the thermal performance of the semiconductor chip package.
It is another object of the present invention to provide a semiconductor chip package comprising a lead frame and a die enclosed in a plastic package body, wherein predetermined portions of the surface of the lead frame are provided with a cupric oxide coating for enhancing the adhesion between the lead frame and the plastic package body.
A semiconductor chip package in accordance with a preferred embodiment of the present invention generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a window pad having an opening defined therein and a plurality of leads having inner ends defining a central area. The window pad is connected to the lead frame by connecting bars and disposed within the central area. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The plastic package body encapsulates the lead frame, the semiconductor die and the bonding wires wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.
Since the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body, the heat generated from the die during normal operation can be directly dissipated by convection and radiation from the backside surface of the die and the lower surface of the lead frame to the surrounding air and the outside environment thereby enhancing the thermal performance of the semiconductor chip package of the present invention.
In a semiconductor chip package in accordance with another preferred embodiment of the present invention, the lead frame has a cupric oxide coating formed on the predetermined portions of the surface thereof. Since the cupric oxide coating has a contour of roughness, the bonding mechanism of the interface between the cupric oxide coating and the plastic package body includes chemical bonding as well as mechanical interlock thereby greatly enhancing the adhesion between the lead frame and the plastic package body. Accordingly, the probability of delamination of the metal-plastic interface is significantly reduced such that the moisture from surrounding can be prevented from directly diffusing through the exposed bond line between the lead frame and the package body into the semiconductor chip package.
The present invention further provides a method for producing a semiconductor chip package comprising the steps of: (A) attaching a adhesive tape to a surface of a lead frame in a manner that an opening of a window pad of the lead frame is covered by the adhesive tape; (B) attaching a semiconductor die to the adhesive tape within the opening of the window pad; (C) electrically coupling the semiconductor die to the lead frame; (D) encapsulating the lead frame and the semiconductor die in a plastic package body; and (E) removing the adhesive tape to expose a lower surface of the lead frame and the backside of the die.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5252855 (1993-10-01), Ogawa et al.
patent: 5776800 (1998-07-01), Hamburgen et al.
patent: 5780931 (1998-07-01), Shimoda et al.
patent: 5894108 (1999-04-01), Mostafazadeh et al.
patent: 6194250 (2001-02-01), Melton et al.
patent: 401315169 (1989-12-01), None

Affiliated with

Also associated with

Rating

Semiconductor chip package and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor chip package and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip package and manufacturing method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2951266