Semiconductor chip package

Details Semiconductor chip package Semiconductor chip package

1997-02-20

2001-03-06

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S730000, C257S778000, C257S787000

Reexamination Certificate

active

06198172

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates generally to testing semiconductor chip packages and particularly relates to an independently aligning semiconductor chip package, and method of using same, which economically improves the testing thereof.
2. The Relevant Technology
Financial incentives arc ever present in all facets of the semiconductor chip industry to reduce material and labor burdens for each individual semiconductor chip produced. One facet readily receptive to improvements is electrical testing. Electrical testing, among other things, examines whether the electrical properties of the active devices of each semiconductor chip meet, exceed or fail defined standards of electrical integrity for the active devices. As such, not only are improvements embraced in the chip industry for new developments that increase the approval rates of semiconductor chips meeting or exceeding those defined standards, but so are developments that increase labor productivity while reducing material costs in the actual testing processes and procedures themselves.
In the past, the testing processes and procedures were not complicated since semiconductor chips had conductive leads extending from the active devices that were of sufficient strength, thickness and pitch, i.e., center-to-center distances between adjacent leads (often around 100 mils), and testing equipment could be directly attached onto the conductive leads. In this manner, however, inefficiencies were realized because labor was manual and the overall size of the chip package necessitated excessive materials.
Although conventional chip packages now have reduced in size, which equates to lower materials costs, the chips are no longer able to physically withstand direct attachment of testing equipment because their leads are less rigid, thinner and often have a pitch around 0.7 mm or less. An external structure, however, is often attached to the packages to provide support and alleviate inherent disadvantages during the testing of the active devices.
Smaller leads also cause alignment problems for modern testing equipment and processes. Because of their small pitch, testing contacts, which electrically mate with the leads, cannot now, without a high degree of alignment precision, be applied in the general direction of the leads, as with the antiquated leads having large pitch, and still have the proper test contact achieve an electrical contact with the proper lead. Even beyond accuracy of alignment, since modern testing is generally automated, the alignment process must be able to quickly and repetitiously align a proper test contact with a proper lead on each chip as numerous chip packages are progressed through the automated testing process.
As seen in
FIG. 1
, the prior art achieves both alignment and support for the conductive leads
16
of a semiconductor chip package
18
by engaging holes
26
in a bracket
28
that supportively surrounding leads
16
with posts
24
on an alignment apparatus
20
. It should be appreciated that alignment apparatus
20
is part of the testing equipment and is generally computer controlled and positioned at a calibrated point in the automated process to ensure accurate alignment between conductive leads
16
and a set of testing contacts
32
if semiconductor chip package
18
is properly arranged thereon. In this illustration, semiconductor chip package
18
is properly arranged because holes
26
and posts
24
, three each, are uniquely positioned such that only one matable position exists therebetween. In addition, each post is arranged with a top portion
29
having a substantially smaller diameter than the diameter of each hole
26
in order to provide ease of mating. The base portions
30
of posts
24
, in contrast, are substantially equal to the diameter of holes
26
to restrict most freedom of movement by chip package
18
once fully seated on alignment apparatus
20
, thereby even further ensuring proper arrangement between chip package
18
and the alignment apparatus
20
.
After properly positioning chip package
18
seen in
FIG. 1
, conductive leads
16
are positioned between a raised surface
36
of alignment apparatus
20
and contacts
32
of a test probe unit
34
to enable electrical testing to be performed upon chip package
18
. Thereafter, contacts
32
, via conductive leads
16
, provide electrical continuity between appropriate testing circuitry within the test probe unit (not shown) and the active devices (not shown). After testing and approval, bracket
28
is detached from its support position about conductive leads
16
and semiconductor chip package
18
is then readied for further processing incident to commercial distribution.
While generally effective, the foregoing requires materials for bracket
28
which are extraneous to the manufacture of the actual semiconductor chip package
18
. In effect, bracket
28
alone, commonly known as a molded carrier ring (MCR), contains more plastic and epoxy molding compound than semiconductor chip package
18
itself. Although the actual material costs of each MCR is minimal per each chip package
18
, material costs become an important factor given production quantities.
Moreover, the foregoing necessitates labor for attaching and detaching bracket
28
which labor is beyond the actual labor of conducting of electrical tests. As such, there is an incentive to find an alternative method of testing.
Concomitantly, the attachment and detachment of bracket
28
, through processing and testing errors, can damage the conductive leads, the chip package and/or the active devices so as to reduce yield. It is, therefore, desirous to increase yield and reduce costs.
SUMMARY OF THE INVENTION
In accordance with the invention as embodied and broadly described herein, an improved semiconductor chip package is provided that is capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The two conforming surfaces are arranged so that only one matable position can be assumed with respect to each other.
In preferred embodiment, a semiconductor chip package has a semiconductor chip with an active device, and a surface on the semiconductor chip having a first region offset from the surface for making a substantially conforming fit with a second region offset from a surface of an alignment fixture such that the semiconductor chip is held stationary relative to the alignment fixture.
Another preferred embodiment is a semiconductor chip for assuming an alignment position with respect to an alignment fixture such that the semiconductor chip is thereby held stationary relative to the alignment fixture. The alignment fixture has thereon a first alignment surface and an alignment plane that is offset from the alignment surface and defined by at least three points. The semiconductor chip includes an active device, a chip surface, and a chip plane that is offset from the chip surface and defined by at least three points The chip plane is parallel to the alignment plane when in the alignment position such that the semiconductor chip is thereby held stationary relative to the alignment fixture.
A still further preferred embodiment is a semiconductor chip package that includes a semiconductor chip having an active area, a plurality of conductive leads electrically connected to the active area, an encapsulating material on the semiconductor chip formed about the plurality of conductive leads, and a region on the encapsulating material that is offset from a surface of the encapsulating material for making a substantially conforming fit with an alignment fixture.
In another preferred embodiment, the substantially conforming surfaces equate to a plurality not less than three substantially conical indentations on the chip

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