Semiconductor chip operating with minimal power consumption

Details Semiconductor chip operating with minimal power consumption Semiconductor chip operating with minimal power consumption

2008-11-17

2011-10-25

Auve, Glenn A (Department: 2111)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S323000

Reexamination Certificate

active

08046618

ABSTRACT:
Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory.

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Hayashi, “Memory architecture of the next generation chip multiprocessor” [online] Jul. 25, 2007, NGArch (Next Generation Architecture) Forum 2007, Document for meeting presentation, Kyushu University, pp. 1 to 17, <https://qir.kyushu-u.ac.jp/dspace/bitstream/2324/9165/1/NGArch2007hayashi.pdf>.
“Memory Architecture for Next-Generation Chip Multiprocessors”, NGArch (Next Generation Architecture) Forum 2007.
Japanese Office Action issued Oct. 12, 2010 for corresponding Japanese Application No. 2007-316938.

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