Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-02
2003-04-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06550047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to the automated generation of input/output (I/O) cells for use in semiconductor integrated chips.
2. Description of the Related Art
In the design of semiconductor integrated circuits, circuit designers commonly utilize what are known as“standard cells” to achieve a particular circuit response. Standard cells are essentially pre-designed layouts of transistors that are wired to perform a certain type of logical function. By way of example, a company, such as Artisan Components, Inc. of Sunnyvale, Calif., designs standard cell libraries incorporating many different types of standard cells, each for performing a specific type of logical operation or operations. The standard cells of the standard cell library are then used by integrated circuit design engineers in conjunction with modeling software to produce a larger scale circuit design that meets a particular specification.
A basic component of designing an integrated circuit of a semiconductor chip is the design of input/output (I/O) cells. As is well known, semiconductor chips have a core region. that is defined in a center portion of a chip and I/O cells that are defined around the core region. I/O pads are then defined along the periphery of the chip surrounding the I/O cells. Conventionally, the I/O pads are selected to follow a defined pad pitch (i.e., spacing between pads). The I/O pads are electrically interconnected to selected I/O cells, which in turn provide access to and from the core region. The I/O cells, as is well known, are designed and selected to meet certain minimum performance characteristic. This is required since particular I/O cells are required to, for example, buffer and condition signals in and out of the core region, provide minimum levels of electrostatic discharge (ESD) protection, and have transistors that can withstand selected voltage tolerances.
Beyond meeting performance characteristics, there is a general desire to have the I/O cells fit in an optimized manner around a given core region. Unless custom designed, pre-designed I/O cells are generally provided as part of a cell library. Cell libraries, as is well known, provide design engineers with a number of choices in cell sizes. One example is I/O cells being 45 microns wide and having its associated. I/O pads arranged in a staggered arrangement. Another example is an I/O cell having a width of 80 microns and its associated I/O cells arranged in an in-line manner. Because I/O cells are required to provide certain performance characteristics, narrower cells, such as the 45 micron cell width, are taller relative to the 80 micron cell width. Therefore, no matter what the selected width may be, the height will have to be adjusted accordingly (either taller or shorter) to ensure that the same amount of transistor area is provided to meet the performance requirement.
Although some optimization is provided by the use of library pre-designed I/O cells and associated I/O pads, a library will generally only provide a few I/O cell options. Thus, a designer will have to select one type of I/O cell option in order to prevent the introduction of white space in the core region of the chip. As defined herein, “white space” is area in the chip in which no devices are formed. That is, the core region of a chip will generally be defined to some arbitrary size depending upon the use and function of the chip being designed. Once the core region is defined, the chip designer will try to optimize the I/O cells (which are defined as a ring around the core region) such that little or no white space is left in the core region. Because the core region can have any size depending upon the application, it is generally very difficult or nearly impossible to match up the ring of I/O cells in a manner that leaves no white space in the core region.
Even though white space may not impact the performance of a chip, the fact that white space is introduced forces the physical size of a silicon chip to be larger that needed. As a result, more expensive wafer space is needed to make the desired chip. This increased cost will generally drive up the cost of the end-product implementation and thus the cost to the consumer. As mentioned above, the I/O cells can be manually designed for each application to provide a better match to a given core region, however, manual design also drives up the cost of the end product since more engineering time is needed to perform the customization.
In view of the foregoing, there is a need for automated I/O generation techniques to enable designers to quickly design I/O cells and I/O pads in a manner that produces good optimization between a chip's I/O region and the chip's core region.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an automated method for generating I/O cells and associated pads for an integrated circuit. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a computer readable media, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, an automated method for generating input/output (I/O) cells for an integrated circuit chip is disclosed. The method includes receiving a width parameter for a desired I/O cell to be used for the integrated circuit chip and then receiving a tolerance parameter for the desired I/O cell. The method then moves to select a cell library having a plurality of slices of equal width. The cell library is selected to meet the tolerance parameter.
Then, the method proceeds to determine a number of the plurality of slices to fit within the width parameter and to satisfy a drive strength parameter. The width parameter is then filled with a first row (or additional stacked rows if needed) of the determined number of the plurality of slices.
In another embodiment, a computer implemented method for automatically generating a custom I/O cell for an I/O region of a semiconductor chip is disclosed. The I/O ring is defined around a core region of the semiconductor chip. The computer implemented method includes providing a selection form (or any computer interface such as a GUI) requesting user input of a desired I/O cell width and performance characteristics. The method then moves to receiving user input from the selection form. A cell slice width for cell slices to be obtained from a cell slice library is selected. The method then proceeds to determine a transistor width requirement to meet the performance requirements and determine a height for the custom I/O cell. The height is selected so as to meet the transistor width requirement while maintaining the desired I/O cell width. The method then moves to filling the desired I/O cell width with one or more of the cell slices having the determined height. The custom I/O cell is configured to at least meet the performance requirements.
In still another embodiment, a method for generating an I/O cell and an associated bond pad is disclosed: The I/O cell and the bond pad are designed to be replicated around a core region of an integrated circuit chip. The method includes receiving a pad pitch parameter and user defined performance characteristics. The performance characteristics include a drive strength parameter. Then, the method moves to receiving a selection of one of an in-line pad arrangement and a staggered pad arrangement. The method then generates an I/O cell having the I/O cell width and a configured height, the configured height is defined to meet the performance characteristics.
In another embodiment, a computer readable media containing program instructions for generating input/output (I/O) cells for an integrated circuit chip is disclosed. The computer readable media includes: (a) program instructions for receiving a width parameter for a desired I/O cell to be used for the integrated circuit chip; (b) program instructions for r
Artisan Components Inc.
Martine & Penilla LLP
Siek Vuthe
Thompson A. M.
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