Semiconductor chip I/O and power pin arrangement

Details Semiconductor chip I/O and power pin arrangement Semiconductor chip I/O and power pin arrangement

1997-08-04

1998-06-16

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257691, 257773, H01L 2348

Patent

active

057675830

ABSTRACT:
A semiconductor device including outer pins including power pins adapted to supply a source voltage or a ground voltage, data pins adapted to input and output data and classified into a plurality of data pin groups having the same number of data pins, and output voltage pins adapted to supply output voltages of data pins of the data pin groups respectively associated therewith, wherein each of the output voltage pins is arranged between a pair of sub-groups constituting one of the data pin groups associated therewith, thereby capable of minimizing a resistance generated between each output voltage pin and each of data pins driven by the output voltage pin and achieving an improvement in data output characteristic.

REFERENCES:
patent: 5473198 (1995-12-01), Hagiya et al.

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