Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2002-06-21
2003-07-08
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S691000, C257S203000, C257S207000, C257S208000, C257S693000, C257S783000, C257S737000, C257S788000, C257S774000, C438S754000, C438S614000, C324S076490, C324S755090, C029S840000
Reexamination Certificate
active
06590297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip (hereinafter, called LSI) with a pad part connected between an integrated circuit and an external circuit so as to output/input a signal to/from the integrated circuit.
2. Description of the Related Art
FIGS.
8
(
a
) through
8
(
c
) are plan views showing a conventional LSI. FIG.
8
(
a
) is a view showing a layout of pads in the LSI, FIG.
8
(
b
) is an enlarged view of a part indicated by “A” in FIG.
8
(
a
), and FIG.
8
(
c
) is a view showing a connection condition in FIG.
8
(
a
).
In this LSI
10
, an integrated circuit not shown is formed on a substrate, and a plurality of wiring patterns are formed to input/output a signal from/to the integrated circuit. Plural pads
11
to be terminals are formed in the plural wiring patterns. The surface of the LSI
10
is covered by a protective film
12
. The protective film
12
is partially removed at parts corresponding to the plural pads
11
so as to form windows
13
. Plural pad parts
14
are formed in a manner that each pad part
14
consists of the window
13
and the pad
11
exposed from the window
13
.
These pad parts
14
are used for wire bonding. As shown in FIG.
8
(
c
), the pad
11
exposed from the window
13
in the pad part
14
is connected with an external circuit through a wire
15
, whereby the external circuit and the LSI are assembled.
FIGS.
9
(
a
) through
9
(
c
) are plan views showing another conventional LSI. FIG.
9
(
a
) is a view showing a layout of pads in the LSI, FIG.
9
(
b
) is an enlarged view of a part indicated by B in FIG.
9
(
a
), and FIG.
9
(
c
) is a view showing a connection condition in FIG.
9
(
a
).
In this LSI
20
, an integrated circuit such as the same integrated circuit in the LSI
1
is formed on a substrate, and a plurality of wiring patterns are formed. Plural pads
11
to be terminals are formed in the plural wiring patterns similarly to the LSI
10
. The surface of the LSI
20
is covered by a protective film
21
. The protective film
21
is partially removed at parts corresponding to the plural pads
11
so as to form windows
23
as shown in FIG.
9
(
b
). A bump
22
of material such as solder is deposited on the pad exposed from the window
23
, and the pad
11
further projects from the surface of the protective film
21
. A pad part
25
consists of the window
23
and the bump
22
.
As shown in FIG.
9
(
c
), the LSI
20
is directly connected to an external circuit
26
with the bump
22
of the pad part
25
, whereby assembly is executed by the TAB (Tape Automated Bonding) method or the COG (Chip On Glass) method.
However, the conventional LSIs have the following problems. Each LSI
10
,
20
has only one connection method for connecting to an external circuit in accordance with each structure of the pad
14
,
25
. Thus, though the integrated circuit and the wiring pattern of the LSI
10
are similar to those of the LSI
20
and the LSI
10
operates similarly to the LSI
20
, it is possible to use only one assembly method based on each structure of the pad part
14
,
25
. As a result, it is necessary to separately manufacture the LSI
10
which is connected to the external circuit by wire bonding and the LSI
20
which is connected to the external circuit by the TAB method, therefore, it is impossible to improve development efficiency and mass production effect.
SUMMARY OF THE INVENTION
To solve the above described problems, the first aspect of the present invention is a semiconductor device comprising (a) a substrate on which an integrated circuit and a plurality of terminals inputting/outputting a signal to/from the integrated circuit are formed, (b) a film covering a surface of the substrate over the terminals, said film having a plurality of groups of at least two apertures, each of said groups formed at a position corresponding to each of the terminals, and (c) a plurality of pad parts connecting with an external circuit, each of said pad parts including at least a first junction being exposed through one aperture so as to be connected with the external circuit via a wire and a second junction provided with conductive material and projecting from another aperture so as to be connected with the external circuit via the conductive material.
In the second aspect of the present invention, the first junction and the second junction may be selectively connected to the external circuit.
The third aspect is a semiconductor chip comprising, (a) a substrate on which an integrated circuit and a plurality of terminals inputting/outputting a signal to/from the integrated circuit are formed, (b) a film covering a surface of the substrate over the terminals, said film having a plurality of groups of at least two apertures, each of said groups formed at a position corresponding to each of the terminals, and (c) a plurality of pad parts connecting with an external circuit, each of said pad parts including at least a first junction structured by exposing the terminal from one aperture and a second junction structured by adding conductive material so as to project from another aperture.
In the fourth aspect, the second junction may be arranged near a center of the substrate rather than the first junction.
In the fifth aspect, at least one of said pad part may include a plurality of the first junctions.
In the sixth aspect, at least one of said pad parts includes a plurality of the second junctions.
According to the first through sixth aspects, in the first junction of each pad part, the terminal exposed from the aperture is connected to a wire by wire bonding, whereby the integrated circuit in the semiconductor chip and the external circuit are connected. In the second junction, the conductive material deposited on the terminal so as to project from the aperture is directly connected to the external circuit and a device by the TAB method and the COG method, whereby the external circuit and the integrated circuit in the LSI are connected. As a result, it is possible to select an assembly method among plural methods without changing the structure of the LSI. Accordingly, the above described problem can be solved.
According to the present invention, each pad part connecting each terminal in the LSI and the external circuit is provided with the first junction connected to the external circuit by wire bonding and the second junction formed by depositing conductive material that is directly connected to the external circuit. As a result, it is possible to select a method among plural assembly methods, and it is possible to assemble LSI on demand without changing the LSI. Thus, it is possible to improve development efficiency and mass production efficiency for the LSI.
Moreover, the plural pad parts are arranged so as to have the first junction at the outside and so as to have the second junction at the center side. As a result, in addition to the above mentioned effects, it is possible to use an assembly method such as wire bonding and an assembly method such as the TAB method and the COG method at the same time. Further, a device can be mounted on the LSI while the LSI is connected to the external circuit by wire bonding, so that it is possible to miniaturize a system to which the LSI is fabricated.
Further, pad parts are provided with a plurality of the first junctions or the second junctions, thus it is possible to increase the number of available assembly methods.
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patent: 60085
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
Williams Alexander O.
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