Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-03-28
2006-03-28
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S405000, C438S479000
Reexamination Certificate
active
07018904
ABSTRACT:
A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
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Mizushima Ichiro
Nagano Hajime
Nitta Shinichi
Oyamatsu Hisato
Sato Tsutomu
Kabushiki Kaisha Toshiba
Malsawma Lex H.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Smith Matthew
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