Semiconductor chip having both polycide and salicide gates...

Details Semiconductor chip having both polycide and salicide gates... Semiconductor chip having both polycide and salicide gates...

2002-08-22

2004-02-03

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S649000, C438S651000, C438S682000, C438S683000

Reexamination Certificate

active

06686276

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of gate electrodes of a semiconductor device. More specifically, the present invention relates to the fabrication of transistors having polycide and salicide gate electrodes on the same semiconductor chip.
BACKGROUND OF THE INVENTION
FIG. 1
is a cross sectional view of a conventional n-channel field effect transistor
100
. Transistor
100
, which is formed in semiconductor substrate
101
, includes n+ type source and drain regions
102
and
103
, p-type channel region
104
, gate oxide layer
105
, conductively doped polycrystalline silicon (polysilicon) layer
106
and tungsten silicide (WSi) layer
107
. Together, polysilicon layer
106
and tungsten silicide layer
107
form a gate electrode
108
. The combined polysilicontungsten silicide structure is commonly referred to as polycide. Polycide is typically formed by depositing a blanket layer of polysilicon, and then depositing a layer of refractory metal silicide, such as tungsten silicide, over the polysilicon layer. The resulting structure is then annealed and etched to form the desired conductive elements (e.g., gate electrodes).
FIG. 2
is a cross sectional view of a conventional n-channel field effect transistor
200
. Transistor
200
, which is formed in semiconductor substrate
201
, includes n+ type source and drain regions
202
and
203
, p-type channel region
204
, gate oxide layer
205
, polysilicon layer
206
and titanium silicide (TiSi) layers
207
S,
207
G, and
207
D. Together, polysilicon layer
206
and titanium silicide layer
207
G form a gate electrode
208
. The combined polysilicon/titanium silicide structure is commonly referred to as salicide. Note that titanium silicide layers
207
S and
207
D are located over source and drain regions
202
and
203
, respectively. Titanium silicide layers
207
S and
207
D reduce the contact resistance to source and drain regions
202
and
203
respectively. The salicide layers are typically formed by exposing the upper surfaces of source region
202
, drain region
203
, and polysilicon layer
206
. A layer of titanium is then blanket deposited over the resulting structure. A heat treatment is then performed, causing the titanium to react with the underlying regions of polysilicon and silicon (i.e., source region
202
, drain region
203
and polysilicon layer
206
), thereby forming titanium silicide layers
207
S,
207
G, and
207
D. As a result, the silicide layers
207
S,
207
G, and
207
D are self-aligned with the underlying silicon regions. Self-aligned silicide layers are usually referred to as salicide layers. Thus, titanium silicide layers
207
S,
207
G, and
207
D, are usually referred to as titanium salicide layers.
The processing requirements of polycide and salicide gate electrodes are inconsistent with one another. As a result, these two types of gate electrodes are not typically used on the same chip. Moreover, there has been no motivation to use both types of gate electrodes on the same chip. However, it may become desirable to have methods for forming both polycide and salicide gate electrodes on the same chip.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides efficient processes for fabricating transistors having polycide gates and transistors having salicide gates on the same wafer. Specifically, in accordance with one embodiment of the present invention, a gate oxide layer or multiple gate oxide layers are formed on a semiconductor substrate. Then, a polysilicon layer having a first portion and a second portion is deposited over the gate oxide layer. A first dielectric layer is formed on the second portion of the polysilicon layer. A metal silicide layer is deposited over the first portion of the polysilicon layer and the first dielectric layer. The portion of the metal silicide layer over the first dielectric is removed. Then, the first dielectric layer is also removed. The metal silicide layer and the polysilicon layer are etched to form one or more polycide gate electrodes and one or more polysilicon gates.
Source and drain regions for the transistors are formed using conventional techniques. Then a second dielectric layer is formed over the polycide gate electrodes and the source and drain regions of the polycide gate transistors. A metal layer is deposited over the resulting structure. The metal layer is reacted to form salicide layers with silicon in contact with the metal layer. Specifically, salicide layers are formed over the polysilicon gates and the source and drain regions of the salicide gate transistors.
The above-described process steps advantageously enable transistors having polycide gates and transistors having salicide gates to be fabricated on the same semiconductor device. The present invention will be more fully understood in view of the following description and drawings.


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