Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-11
2004-02-03
Flynn, Nathan J. (Department: 2820)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06686617
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of semiconductor chips and, more specifically, to the fabrication of both compact memory and high performance logic on the same semiconductor chip.
BACKGROUND OF THE INVENTION
Embedded memory, such as embedded dynamic random access memory (DRAM), is one of the fastest growing segments of the semiconductor industry. Two types of embedded DRAM processes currently exist: one that makes compact DRAM cells and low performance logic, and another that makes large DRAM cells and high performance logic. Embedded static random access memory (SRAM) processes also offer only compact SRAM cells with low performance logic or large SRAM cells with high performance logic. Thus, it is desirable to provide a process for manufacturing both compact embedded memory, such as compact DRAM or SRAM cells, and high performance logic, on the same chip.
In particular, in certain advanced DRAM processes, the memory gate stack has a nitride film on top, which allows a borderless contact to be made to the gate in a memory cell. On the other hand, certain high performance logic processes do not provide such a thick nitride film on top of the logic gate stack. The reason for this configuration is that a tall polysilicon-nitride stack would compromise across-chip linewidth variation (ACLV), which is a key parameter in maintaining the high performance desired in high performance logic.
Also, in many processes for combined logic and memory, the polysilicon gates in both regions are created simultaneously, as are the sidewall oxides. Because the optimum characteristics of gate and memory sidewall oxides are mutually exclusive (thin logic sidewall oxides and thick memory sidewall oxides are optimal), the sidewall oxides created simultaneously tend to reflect a compromise in characteristics which is not optimal for either region. In addition, logic well implants tend to be created at the same time as memory well implants, meaning that the logic well implants are subject to degradation during memory processing. Therefore, the combination of memory and logic processes has not resulted in optimal structural characteristics for either the memory or logic regions.
The deficiencies of the conventional semiconductor chip manufacturing processes show that a need still exists for a combined memory and logic creation process that provides the structural characteristics typically provided by stand-alone high performance logic processes and stand-alone compact embedded memory processes. To overcome the shortcomings of the conventional processes, a new process is provided. An object of the present invention is to provide a process that is compatible both with an advanced DRAM process that creates memory cells with nitride films on top, allowing a borderless contact between the gate and memory cell, and with a high performance logic process that creates a logic device without such a nitride film on top.
Another object of the present invention is to provide a process that forms the memory sidewall oxide as a step completely decoupled from the formation of the logic sidewall oxide. Thus, the memory sidewall oxide may be tailored for improved memory retention characteristics whereas the logic sidewall oxide may be tailored for improved logic device performance. Still another object of the present invention is to provide a process that completes the entire set of memory processing steps before the logic well implants are created. A related object is to prevent any substantial degradation in the logic device due to exposure to high temperature memory processing steps. It is yet another object of the present invention to provide a process in which the BPSG layer is deposited before logic gate formation. A related object is to permit densification of the BPSG layer at high temperature (thus allowing a tight-pitch memory array) without adversely affecting the logic devices.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a double polysilicon process for fabricating a semiconductor chip having a memory device and a logic device on the same chip. The process comprises providing a substrate having a top surface, a memory region, a logic region, and a pad nitride layer overlaying at least the logic region. The substrate also has a plurality of shallow trench isolation trenches.
The process further comprises forming the memory device in the memory region (including the first polysilicon and other gate layer deposition and etching steps, and a sidewall oxidation step), then applying first a spacer nitride layer and second a protective layer over both the memory region and the logic region, and then removing the protective layer over the logic region to expose the substrate. Next, the logic device is formed in the logic region (including the second polysilicon deposition and etching step, and a sidewall oxidation step). The step of forming the logic device also includes applying a metal, such as cobalt or titanium, over all horizontal surfaces in the logic region and conducting an annealing step sufficient for the metal to form a metal salicide where the metal rests over silicon or polysilicon regions. Unreacted metal over non-silicon and non-polysilicon regions may be later removed.
The memory devices may be protected during the salicidation step by depositing a nitride layer over both the memory region and the logic region and then removing the nitride layer from the logic region before applying the metal to the logic device. In another embodiment, an oxide layer protects the memory device during salicidation. In yet another embodiment, a Boro-Phospho Silicate Glass (BPSG) layer is first applied, densified, and etched to remain only over the memory region before logic gate formation. In each embodiment, an uppermost nitride layer is deposited after applying the metal to the logic device, and a dielectric layer is then deposited over the nitride layer.
The present invention also encompasses a semiconductor chip comprising at least one embedded memory device and at least one high performance logic device produced according to the process outlined above. The embedded memory device may compromise a memory gate stack having an n-type polysilicon layer, a tungsten-containing layer (such as tungsten silicide or tungsten-tungsten nitride) on top of the polysilicon layer, and a silicon nitride cap layer on top of the tungsten silicide layer. The high performance logic device may comprise a logic gate stack having a polysilicon layer and a cobalt or titanium salicide layer on top of the polysilicon layer.
In one embodiment, the memory gate stack may comprise: the n-type polysilicon layer, the tungsten-containing layer, and the silicon nitride cap layer, each layer having at least one sidewall; a sidewall oxide tuned for memory-retention characteristics over the sidewalls of the n-type polysilicon layer and, optionally, over the tungsten-containing layer; and a nitride sidewall spacer covering the oxide and silicon nitride cap layer.
The logic gate stack may consist essentially of: the polysilicon layer having a top surface and a sidewall, a sidewall oxide over the polysilicon layer sidewall and having a horizontal surface level with the polysilicon layer top surface, a nitride logic spacer over the sidewall oxide and over a portion of the substrate immediately adjacent the logic gate stack and having one or more horizontal surfaces parallel to the substrate top surface, and the cobalt or titanium salicide layer over the polysilicon layer and the horizontal surface of the sidewall oxide. The chip may further comprise a nitride layer over the memory region, a cobalt or titanium salicide layer over the substrate top surface in the logic region, one or more logic shallow trench isolations in the logic region, and at least one border shallow trench isolation separating the logic region from the memory region.
In another embodiment, the chip may comprise a memory BPSG filler over the nitride layer in the memory reg
Agnello Paul D.
Chen Bomy A.
Crowder Scott W.
Divakaruni Ramachandra
Iyer Subramanian S.
Flynn Nathan J.
International Business Machines - Corporation
Quinto Kevin
Schnurmann H. Daniel
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