Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-07-18
2004-01-27
Dang, Phuc T. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S692000
Reexamination Certificate
active
06683369
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 2001-219182, filed Jul. 19, 2001, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor chip, more particularly to a semiconductor chip having a support member. The invention further relates to a tape substrate, more particularly to a tape substrate having a support member. Moreover, the invention relates to a semiconductor package having the semiconductor chip and the tape substrate. Furthermore, the invention relates to a method of manufacturing the semiconductor chip and the semiconductor package.
2. Description of the Related Art
Referring to
FIG. 20
, a semiconductor chip
1
of the related arts, which is used for a semiconductor package, includes a single supporting member
4
, pads
2
, bump electrodes
3
, each of which is formed on one of the pads
2
. The pads
2
are formed on a single surface of the semiconductor chip
1
, and the pads
2
are electrically connected to circuits formed in the semiconductor chip
1
. The pads
2
are disposed in an area
30
along the side of the semiconductor chip
1
. Each of the bump electrodes
3
has a top surface
3
a
and a height. An area of the top surface
3
a
of the bump electrode
3
is determined by assemble characteristics and a connecting resistance, and the height of the bump electrode
3
is determined by the reliability of the connection.
The semiconductor chip
1
is connected to a tape substrate
5
, which is illustrated in
FIG. 21
, by a face-down bonding. The tape substrate includes land electrodes
6
to be connected to the bump electrodes
3
of the semiconductor chip
1
, I/O lead electrodes
14
, and wiring patterns
13
, each of which connects one of the land electrodes
6
to one of the I/O lead electrodes
14
. The shape of each land electrode
6
is determined by consideration of the reliability of the connection and the arraignment with the bump electrode
3
. In this illustrative structure, the land electrode
6
is square. The surface of the land electrode may be metal plated. Generally, the number of bump electrodes
3
is the same as that of the land electrodes
6
. Thus, each of the bump electrodes
3
corresponds to one of the land electrodes
6
. Therefore, the positions of the land electrodes
6
are determined by the positions of the bump electrodes
3
.
Referring to
FIG. 22
, the bump electrodes
3
of the semiconductor chip
1
are aligned with the land electrodes
6
of the tape substrate
5
, and then, the semiconductor chip
1
is fixed on the tape substrate
5
by the face-down bonding using a conductive paste. The semiconductor chip
1
may be fixed on the tape substrate
5
using a thermal compression method. By the process described above, the semiconductor chip
1
is connected to the tape substrate
5
electrically and physically.
Then, as shown in
FIG. 23
, resin material
7
is injected from the side of the semiconductor chip
1
into a gap formed between the semiconductor chip
1
and the tape substrate
5
. The resin material
7
goes into the gap by the capillary phenomenon until the gap is filled A semiconductor package
70
shown in
FIG. 24
is completed by the above described process. In the process for manufacturing the semiconductor package
70
, it is important to completely fill the gap with the resin material
7
without creating void as shown in FIG.
25
.
After that, external land electrodes
6
a
, which are electrically connected to the land electrodes
6
by wiring pattern
13
, I/O leads
14
, and internal wires formed in the tape substrate
5
, are formed on the back surface of the tape substrate
5
. Then, a solder ball
8
is formed on each of the external land electrodes
6
a
. As a result, a tape BGA type semiconductor package illustrated in
FIG. 26
is completed.
However, as shown in
FIG. 27
, according to the tape BGA type semiconductor package having the structure described above, the tape substrate
5
is transformed during the process in which the semiconductor chip
1
is fixed on the tape substrate, because of the influence of heat or pressure. When the tape substrate
5
is transformed, the following problems occur.
(1) The gap between the tape substrate
5
and the semiconductor chip
1
may not be filled with the resin material
7
completely because the gap narrows. Even if the gap between the tape substrate
9
and the semiconductor chip
1
is filled with the resin material
7
completely, the thickness of the resin material
7
may not be sufficient in some parts of the gap. As a result, water vapor resistance and strength of transverse may be decreased, and light blocking effect may also be reduced so that the semiconductor chip may malfunction.
(2) In the tape BGA structure, the length from the external land electrode
6
a
to the surface of an assemble substrate
9
on which the semiconductor package is mounted, varies so that some solder balls
8
may not reach terminals formed on the assemble substrate
9
.
SUMMARY OF THE INVENTION
An objective of the invention is to resolve the above-described problem and to provide a semiconductor chip having a support member, a tape substrate, a semiconductor package having the chip and the substrate and a method of manufacturing them.
The objective is achieved by a semiconductor chip having a substrate including a main surface, the substrate including on the main surface a flame-shaped first area, which is along sides, and a second area encompassed by the first area, a pad formed in the first area, a bump electrode formed on the pad and at least one supporting member formed on the second area.
The objective is further achieved by a tape substrate having a tape including a main surface, the tape including a flame-shaped first area on the main surface, and a second area encompassed by the first area, a land electrode formed in the first area, an I/O electrode formed in the first area, a wiring pattern formed in the first area, the wiring pattern connecting the land electrode to the I/O electrode, a resist pattern formed on the wiring patter, and at least one supporting member formed in the second area.
The objective is moreover achieved by a semiconductor package having the semiconductor chip described above, a tape substrate, which has a main surface and a buck surface opposite to the main surface, having a land electrode on the main surface, the land electrode is connected to the bump electrode, and resin material introduced into a gap, which is formed between the substrate and the tape substrate.
The objective is achieved by a method of manufacturing a semiconductor chip having providing a substrate having a main surface, the substrate including on the main surface a flame-shaped first area, which is along sides, and a second area encompassed by the first area, forming a pad in the first area, forming a bump electrode on the pad, and forming at least one supporting member on the second area.
REFERENCES:
patent: 5635756 (1997-06-01), Kohno et al.
patent: 6208022 (2001-03-01), Tamura
patent: 8-46313 (1996-02-01), None
patent: 11-87423 (1999-03-01), None
patent: 2000-195900 (2000-07-01), None
patent: 2000-243785 (2000-09-01), None
patent: 2001-110951 (2001-04-01), None
Dang Phuc T.
Mimura Junichi
Oki Electric Industry Co. Ltd.
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