Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1998-09-15
2001-03-13
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S691000
Reexamination Certificate
active
06201308
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a low-noise ground line and, more particularly, to a structure for reducing the noise propagating through the ground line in a semiconductor device.
(b) Description of the Related Art
A semiconductor device generally has a pair of source lines including a high voltage source line and a ground line for supplying electric power to the functional elements disposed therein. Referring to
FIG. 1
which shows a schematic top plan view of a first conventional semiconductor chip, the semiconductor chip is implemented as a SRAM device and formed on a p-type silicon substrate. The semiconductor chip
10
has a scribe region
12
on the outer periphery of the chip
10
, wherein a ground line
13
shown by hatching is disposed. In the internal area of the semiconductor chip
10
, another ground line
14
shown also by hatching is disposed for supplying a ground potential to the functional elements in the internal area. Both the ground lines
13
and
14
are connected together through bonding pads
14
A and
14
B.
A high voltage source line
15
is disposed in the internal area for supplying a source potential to the internal circuit, and connected to an external lead frame (not shown) through bonding pads
15
A and
15
B disposed at the ends of the source line
15
, by using a bonding technique. The ground lines
13
and
14
are also connected to the external lead frame through bonding pads
14
A and
14
B disposed at the ends of the ground lines
13
and
14
, by using a bonding technique.
I/O circuit
16
is disposed as a part of the internal circuit adjacent to the scribe region
12
of the semiconductor chip
10
. The I/O circuit
16
includes a plurality of output transistors
19
A to
19
F, which are connected to a common ground line
17
for the I/O circuit
16
, source line
18
and corresponding signal lines not shown in the figure. The signal lines are connected to the external lead frame through bonding pads by a bonding technique for outputting corresponding signals from the output transistors. The ground line
17
and the source line
18
are connected to bonding pads
17
A and
18
A, respectively, which are connected to external lead frame for receiving the ground potential and the source potential.
With the recent increase in the operational speed of the semiconductor device, it has become difficult to obtain a stable operation of the semiconductor chip of
FIG. 1
due to the adverse effect of the noise reflected during signal transmission from the output transistors. For reducing the adverse effect, it may be required that the ground line
17
disposed for the output transistors
19
A to
19
F have a larger width for suppressing the fluctuation of the ground potential on the ground line
17
. However, the demand for reduction of the chip size for the semiconductor device in the recent years prevents a large width for the ground line
17
, which leads an unstable operation of the semiconductor device.
Referring to
FIG. 2
which shows a top plan view of a corner portion of a typical DRAM formed on an n-type semiconductor substrate as a second conventional semiconductor chip
20
, a first stage circuit block
25
as a part of the internal circuit is disposed in vicinity of the outer periphery of the semiconductor chip, wherein ground lines
23
and
24
extend parallel to each other.
FIG. 3
shows a circuit configuration for the input stage circuit block
25
shown in
FIG. 2
, wherein p-channel transistors Q
1
and Q
2
and an n-channel transistor Q
3
are connected in series between a high voltage source line Vcc and the ground line. An address terminal connected to the gates of transistors Q
2
and Q
3
is connected to the bonding pad
27
A through the electrostatic discharge element
26
A as shown in FIG.
2
. If another address terminal is disposed in the first stage circuit block
25
, the another address terminal is similarly connected to the bonding pad
27
B through the electrostatic discharge element
26
B as shown in FIG.
2
.
The bonding pads
27
A and
27
B are respectively connected to the external lead frame by a bonding technique for connecting the address terminals to the external lead frame. The electrostatic discharge elements
26
A and
26
B are connected to the ground line
24
for protecting the semiconductor device against destruction of the transistors caused by the electrostatic discharge failure. The ground line
23
disposed on the scribe region
22
is connected to the ground line
24
through a bonding pad
24
A, which is connected to the external lead frame by a bonding technique. In
FIG. 2
, the recent increase in the operational speed of the semiconductor device also causes the ground potential of the ground line
24
to fluctuate due to the noise on the ground line
24
.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a semiconductor device wherein fluctuation of the ground potential and/or the source potential of the semiconductor device can be suppressed.
The present invention provides, in a first aspect thereof, a semiconductor chip comprising a semiconductor substrate including an internal circuit region and a scribe region encircling the internal circuit region, the internal circuit region receiving therein an internal circuit and an I/O circuit for inputting an external signal to supply an internal signal to the internal circuit, a first source line disposed in the internal circuit region for applying a first potential to the internal circuit, a second source line formed on the scribe region and connected to the first source line via a bonding pad for applying the first potential to the semiconductor substrate, and a third source line connected to the second source line without passing the bonding pad for applying the first potential to the I/O circuit.
The present invention provides, in a second aspect thereof, a semiconductor chip comprising a semiconductor substrate including an internal circuit region and a scribe region encircling the internal circuit region, the internal circuit region receiving therein an internal circuit and an I/O circuit for inputting an external signal to supply an internal signal to the internal circuit, a first source line disposed in the internal circuit region for applying a first potential to the internal circuit, a second source line formed on the scribe region and connected to the first source line via a bonding pad for applying the first potential to the semiconductor substrate, the first source line having a first portion directly connected to the I/O circuit and to a second portion of the second source line without passing the bonding pad.
In accordance with the semiconductor devices of the present invention, a ground line or high voltage source line disposed for the internal circuit as one of the source lines is less susceptible to noise generated by the I/O circuit, whereby a stable operation of the semiconductor chip can be obtained.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 5875086 (1999-02-01), Narita
patent: 61-268034 (1986-11-01), None
patent: 2-211653 (1990-08-01), None
patent: 2-254740 (1990-10-01), None
patent: 7-297372 (1995-11-01), None
patent: 9-199670 (1997-07-01), None
Hirota Takuya
Ikegami Kayoko
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
Loke Steven
NEC Corporation
Tran Thien F.
LandOfFree
Semiconductor chip having a low-noise ground line does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor chip having a low-noise ground line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip having a low-noise ground line will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455812