Semiconductor chip ground noise immunity testing system and...

Details Semiconductor chip ground noise immunity testing system and... Semiconductor chip ground noise immunity testing system and...

1999-12-09

2002-08-06

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06429676

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a tester of a semiconductor chip, and more particularly to a semiconductor chip testing system and a tester for testing immunity from ground noise of the semiconductor chip.
BACKGROUND OF THE INVENTION
As semiconductor chips achieve higher speeds and higher integration, they are more susceptible to a ground bounce phenomenon. Ground bounce results from stray inductances in signal lines and current changes during high speed switching. Moreover, the ground level varies in relation to crosstalk caused by mutual inductance and capacitance between signal lines. These phenomena are called ground noise.
In addition, ground noise immunity means resistance to a noise generating environment, that is, a function of a chip which can normally perform its operations in spite of the noise generated inside or outside the chip when the chip is packaged and assembled to operate within a circuit or electronic system.
For conventional testers a ground voltage is applied to a terminal of the chip from the ground of the tester, so that there is almost no possibility that noise is induced into the ground voltage applying terminal of the chip. However, when the semiconductor chip is applied to the actual system, it becomes possible that the noise being generated internally at the system is induced into the ground voltage applying terminal of the chip. Therefore, even if the chip is classified as normal at the time of the test, the semiconductor chip may not function properly due to the ground noise when it is actually assembled into a system.
This is because the conventional tester of the semiconductor chip performs a test without consideration of the ground noise.
Accordingly, a test could be performed by the conventional tester while ground noise is continuously induced into the ground voltage applying terminal of the semiconductor chip. Such testing would more closely simulate operational conditions of the semiconductor chip.
However, there is a problem with this approach. A large current is required to enable the ground noise to be induced into the ground terminal of the semiconductor chip and thus simulate actual operating conditions. Unfortunately, the current driving capacity of a pin driver of the conventional tester is only about 25 mA which is not enough to simulate ground noise when the semiconductor chip is tested. Thus, semiconductor chips continue to be tested without sufficient concern for the real-world problems in operation of induced ground noise.
SUMMARY OF THE INVENTION
It is an object to provide a testing system of a semiconductor chip which can improve reliability of the semiconductor chip by testing ground noise immunity when the semiconductor chip is tested.
It is another object to provide a tester of a semiconductor chip that performs the function of testing the chip's ground noise immunity.
In order to accomplish the aforementioned object, there is provided a semiconductor chip testing system which comprises:
a tester with a predetermined number of pin drivers; and
driving means connected between the pin drivers of the tester and a ground voltage applying terminal of the semiconductor chip to be tested, wherein control signals are applied to the pin drivers according to a testing method of a tester to generate ground noise at the ground voltage applying terminal of the semiconductor chip, thereby performing a test on the semiconductor chip.
In order to accomplish the aforementioned second object, there is provided a tester of the semiconductor chip comprising:
a predetermined number of pin drivers with large current driving capacity; and
a predetermined number of pin drivers with small current driving capacity, wherein control signals are applied to the pin drivers with large current driving capacity according to a test program to apply ground noise to a ground voltage applying terminal of a semiconductor chip to be tested while the semiconductor chip is tested according to the test program.


REFERENCES:
patent: 5418746 (1995-05-01), Choi
patent: 5842155 (1998-11-01), Bryson et al.
patent: 5883521 (1999-03-01), Nishikawa

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