Semiconductor chip for mounting on a semiconductor package subst

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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257690, 257778, 257786, H01L 2941, H01L 23544, H01L 2166

Patent

active

054752361

ABSTRACT:
A semiconductor chip for mounting on a package substrate by a flip-chip process includes a plurality of electrode pads of a first group provided on a major surface of the semiconductor chip for external electrical connection such that the electrode pads of the first group cover a major surface of the semiconductor chip in rows and columns; and a plurality of electrode pads of a second group each having a size substantially larger than the electrode pads of the first group and provided on the major surface of the semiconductor chip in electrical connection with an active part of the semiconductor chip that is used for a burn-in process. Each of the electrode pads of the first group is covered by a solder bump that projects from the major surface of the semiconductor chip a first distance. Each of the electrode pads of the second group is formed of a conductor material having a melting point higher than the solder bump and projecting from the major surface of the semiconductor chip a second distance that is substantially smaller than the first distance.

REFERENCES:
patent: 4774630 (1988-09-01), Reisman et al.
patent: 5212406 (1993-05-01), Reele et al.
IBM Technical Disclosure Bulletin, vol. 27, No. 7B, Dec. 1984, New York US, pp. 4210-4211, Anderson et al. `Extended Pad for Testing Package Parts` *whole document*.
Patent Abstracts of Japan, vol. 15, No. 254 (E-1083)8 Apr. 1991 & JP-A-30 82 129 (Agency of Ind Science & Technol) *abstract*.
Patent Abstracts of Japan, vol. 12, No. 285 (E-642)4 Aug. 1988 & JP-A-63 062 341 (Fujitsu Ltd) 18 Mar. 1988 *abstract*.
Patent Abstracts of Japan, vol. 9, No. 4 (E-288)10 Jan. 1985 & JP-A-59 154 035 (Nippon Denso KK) 3 Sep. 1984 *abstract*.

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