Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-11-10
2003-09-02
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C714S724000, C714S729000, 37
Reexamination Certificate
active
06615289
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an integrated semiconductor chip in which one of a plurality of possible data input/data output organizational forms is preset by externally wiring or interconnecting selected bonding pads to a voltage potential. Due to the preset data input/data output organizational form not all of the bonding pads for an exchange of input data and output data are required for a normal mode operation.
A semiconductor chip usually has internal terminals to one or more integrated circuits situated on the chip, which are referred to as so-called bonding pads. If the semiconductor chip is built into a housing of a semiconductor module, all or some of the bonding pads are provided with bonding wires which are electrically conductively connected to leads to external terminals of the semiconductor module. Such terminals may be, for example, terminals of data lines to external assemblies situated for example on a circuit board outside the module. A semiconductor chip can have different types of internal terminals. By way of example, a distinction is made between data-carrying bonding pads, which serve for the exchange of input and output data (for example via data lines mentioned above), and bonding pads, which, through the use of a type of interconnection or wiring that is to be selected, define for example an operating mode and/or a data input/data output organizational form of the chip. Such bonding pads are referred to as bonding option pads.
Due to the diversity of integrated semiconductor circuits with respect to products and applications, semiconductor chips are not developed and produced exclusively for individual applications, but rather are fundamentally configured for a plurality of applications and are tailored to individual applications by slight adaptations or changes. Thus, by way of example, a specific operating mode or one of a plurality of possible data input/data output organizational forms can be defined subsequently (after the production of the chip) by connecting a specific number or combination of the above-mentioned bonding option pads via an external terminal fixedly to a terminal for an external voltage potential. This connection between external terminal and bonding pad is permanently done by “bonding” (connection of a bonding wire to the respective bonding pad) and can no longer be reversed after the incorporation into the housing of the semiconductor module.
In order to be able to test a semiconductor chip after incorporation into a housing of a semiconductor module, it has so far been necessary to use test methods and test programs which are coordinated with or specific to the chip configuration respectively set through the use of bonding option pads. Depending on the diversity of applications of a semiconductor chip, thus a multiplicity of test methods and test programs results. This multiplicity of test methods and test programs may also vary in terms of the time requirement, depending on the chip configuration that has been set.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor chip configuration which overcomes the above-mentioned disadvantages of the heretofore-known semiconductor chips of this general type and which allows to reduce the number of different variants of the test program and which further allows to reduce the expenditure of time for a test program for testing the semiconductor chip.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor chip configuration of the type having a semiconductor chip with a plurality of bonding pads for an exchange of input data and output data, the plurality of bonding pads including a first group of bonding pads being used for the exchange of input data and output data in a normal mode and including a second group of bonding pads not being used for the exchange of input data and output data in the normal mode, a data input/data output organizational form of a plurality of data input/data output organizational forms being preset for the normal mode, wherein the improvement includes that the first group and the second group of bonding pads for the exchange of input data and output data are connected to respective external terminals; and the semiconductor chip is operable in a test mode and has an altered data input/data output organizational form during the test mode, such that the second group of bonding pads are used in the test mode for the exchange of input data and output data.
In accordance with another feature of the invention, at least one bonding option pad is provided for presetting one of the plurality of data input/data output organizational forms for the normal mode, the at least one bonding option pad has an external interconnection and is fixedly connected with a bonding wire to a respective terminal for an external voltage potential. The semiconductor chip has the altered data input/data output organizational form during the test mode while the external interconnection is not changed.
In accordance with a further feature of the invention, the at least one bonding option pad has an internal interconnection for setting the altered data input/data output organizational form. The internal interconnection cancels an efficacy of the external interconnection of the at least one bonding option pad to the respective terminal for the external voltage potential.
In accordance with yet another feature of the invention, a control device for controlling operating modes is provided. The control device generates a control signal for setting the altered data input/data output organizational form.
In accordance with a yet a further feature of the invention, a circuit is connected to the at least one bonding option pad provided. The circuit includes a first transmission gate having a first field-effect transistor with a drain source path and a gate, having a second field-effect transistor with a drain source path and a gate, having a first coupling node and a second coupling node, the first field-effect transistor being connected to the second field-effect transistor at the first and the second coupling nodes with the drain source path of the first field-effect transistor being connected in parallel to the drain source path of the second field-effect transistor; a second transmission gate having a third field-effect transistor with a drain source path and a gate, having a fourth field-effect transistor with a drain source path and a gate, having a third coupling node and a fourth coupling node, the third field-effect transistor being connected to the fourth field-effect transistor at the third and the fourth coupling nodes with the drain source path of the third field-effect transistor being connected in parallel to the drain source path of the fourth field-effect transistor, the first field-effect transistor having a complementary channel type with respect to the second field-effect transistor, the third field-effect transistor having a complementary channel type with respect to the fourth field-effect transistor, the first coupling node being connected to a reference-ground potential of the semiconductor chip, and the second coupling node forming an output terminal for an output signal for setting one of the plurality of data input/data output organizational forms, the fourth coupling node being connected to the output terminal; an input terminal for receiving a control signal setting the altered data input/data output organizational form, the input terminal being connected to the gate of the first field-effect transistor and to the gate of the fourth field-effect transistor; a first inverter connecting the gate of the second field-effect transistor and the gate of the third field-effect transistor to the input terminal for receiving the control signal; a second inverter connecting the at least one bonding option pad to the third coupling node; and a resistor connected between the at least one bonding option pad
Feurle Robert
Schneider Helmut
Gaffin Jeffrey
Greenberg Laurence A.
Infineon - Technologies AG
Kim Harold
Locher Ralph E.
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