Semiconductor chip carrier package with a heat sink

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

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Details

357 81, 361401, 361414, H05K 720

Patent

active

046301720

ABSTRACT:
A semiconductor chip carrier and contact array package having an apertured dielectric bottom layer (11), one or more chip connection layers such as wire bond layers (16, 17) insulated from one another, at least one chip-holding recess (24) in the wire bond layers and a heat conductive copper heat sink insert (26) extending across the aperture of the dielectric layer and forming a base adapted to be in heat-conductive contact with the bottom of an integrated circuit chip (27) to be attached thereon whereby heat flux generated by the chip is quickly and efficiently removed from the chip body. The wire bond layers (16, 17) contains metallization patterns (29) for bonding to the chip and a grid array of contacts or connection pins (20) connected to plated through-holes in the wire bond layer(s) for plugging the carrier to a circuit board or the like. The various layers of the carrier per se are manufactured by predrilling and aperturing, forming the metallization patterns, stacking and pressure laminating to form a reliable compact structure having high heat dissipation properties.

REFERENCES:
patent: 2942165 (1921-05-01), Jackson et al.
patent: 3365620 (1968-01-01), Butler et al.
patent: 3436604 (1969-04-01), Hyltin et al.
patent: 3436819 (1969-04-01), Lunine
patent: 3777221 (1973-12-01), Tatusko et al.
patent: 3846824 (1974-11-01), Bell
patent: 3958195 (1976-05-01), Johnson
patent: 4338621 (1982-07-01), Braun

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