Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2000-02-07
2004-04-20
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S777000, C257S778000
Reexamination Certificate
active
06724084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip to be applied to a chip-on-chip structure in which semiconductor chips are bonded to each other in a stacked relation and a flip-chip-bonded structure in which a semiconductor chip is bonded to a printed circuit board in a face-to-face relation. The invention further relates to a production method for such a semiconductor chip. The invention still further relates to a semiconductor device having a semiconductor chip bonded to a solid device (another semiconductor chip or an interconnection board).
2. Description of Related Art
For size reduction and higher integration of a semiconductor device, a so-called chip-on-chip structure, for example, is employed in which a plurality of semiconductor chips are bonded to one another in a face-to-face stacked relation.
In the chip-on-chip structure, as shown in
FIG. 25
, semiconductor chips
91
,
92
opposed to each other are spaced a predetermined distance from each other and electrically connected to each other by a plurality of bumps
93
provided therebetween. The semiconductor chips
91
,
92
thus stacked are sealed with a mold resin
94
.
When the semiconductor chips
91
,
92
are sealed with the mold resin
94
, a relatively great pressure is applied to the semiconductor chips by the mold resin
94
. Where the semiconductor chips
91
,
92
are different in thermal expansion coefficient, strains occur in the semiconductor chips
91
,
92
due to stresses exerted thereon when a relatively great amount of heat is applied thereto at the resin sealing. Thus, portions of the semiconductor chips
91
,
92
not supported by the bumps
93
are deformed, resulting in deterioration of the characteristics of devices formed in the semiconductor chips
91
,
92
.
For electrical connection between the semiconductor chips
91
and
92
, at least one of surface protective films covering the semiconductor chips is formed with openings through which portions of internal interconnections are exposed, and the bumps
93
are provided on the exposed portions of the internal interconnections. Therefore, the arrangement of the bumps
93
is restricted by the pattern of the internal interconnections and, in some cases, the bumps
93
are unevenly disposed on the surface of the semiconductor chip in accordance with the internal interconnection pattern. Where the bumps
93
are unevenly disposed on the surface thereof, for example, the chip
92
may be tilted on the underlying chip
91
.
When the chips
91
,
92
are bonded to each other, great stresses are exerted on bump connections. Therefore, the semiconductor substrate provided with the bumps
93
may suffer from a mechanical damage. For prevention of the damage, an attempt has been made to absorb the stresses by utilizing the resilient property of the electrical connection bumps. However, the absorption of the stresses is in sufficient, so that the substrate is damaged. This results in a lower yield.
Further, the substrate often suffers from warpage due to heat applied thereto at mounting of the semiconductor device, so that great stresses are exerted on the bump connections.
The afore said problems are associated not only with the semiconductor device of chip-on-chip structure, but also with a semiconductor device of so-called flip-chip-bonded structure in which a semiconductor chip is bonded to a printed circuit board in a face-to-face opposed relation.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a semiconductor chip which is allowed to exhibit stable device characteristics by prevention of deformation thereof due to stress-strains and the like.
It is a second object of the invention to provide a semiconductor chip which is capable of relieving a stress applied thereto at the bonding thereof.
It is a third object of the invention to provide a semiconductor chip production method which allows an electrical connection portion (functional bump) and a dummy connection portion (dummy bump) to have substantially the same height.
It is a fourth object of the invention to provide a semiconductor device which features reliable connection between a semiconductor chip and a solid device, e.g., another semiconductor chip, and to provide a semiconductor chip for such a semiconductor device.
A semiconductor chip according to the present invention comprises: a semiconductor substrate; a functional bump provided on a surface of the semiconductor substrate for electrical connection between an internal circuit provided on the semiconductor substrate and a solid device; and a dummy bump provided on the surface of the semiconductor substrate and not serving for the electrical connection between the internal circuit and the solid device.
The dummy bump may be a stress relieving bump for relieving a stress applied thereto.
The solid device may be another semiconductor chip or an interconnection board.
The stress relieving bump may be provided in a semiconductor chip formation region or in a peripheral region surrounding the semiconductor chip formation region.
With this arrangement, the bump which does not have the originally intended bump function serves to absorb a shock at the bonding of the chip. Therefore, the substrate is prevented from being damaged at the bonding, so that the semiconductor chip production yield can be improved. During use, the bump connection relieves a stress exerted on the substrate, thereby ensuring the reliability of the semiconductor chip.
The functional bump may be provided on a peripheral portion of a mating surface opposed to the solid device. In this case, the dummy bump is preferably provided on a central portion of the mating surface.
With this arrangement, the central portion of the semiconductor chip can be supported by the dummy dump. Therefore, the deformation of the semiconductor chip can be prevented which may otherwise occur due to a mechanical pressure and a stress-strain. Thus, the semiconductor chip can exhibit stable device characteristics.
The dummy bump preferably has a greater contact area in contact with the solid device than the functional bump.
When the dummy bump is provided on the surface of the semiconductor chip, the dummy bump is preferably formed of the same material as the function bump which serves for electrical connection to another semiconductor chip opposed thereto. Thus, the formation of the dummy bump and the formation of the functional bump can be achieved in the same process step, whereby an increase in the number of the steps of a semiconductor chip production process can be prevented.
In this case, however, there is a problem that the functional bump and the dummy bump have different projection heights. As shown in
FIG. 23
, a bump material is selectively deposited on a surface protective film
193
formed with an opening
192
through which an interconnection
191
is partly exposed. Thus, a functional bump
194
and a dummy bump
195
are formed on the opening
192
and on the surface protective film
193
, respectively. In this case, a portion of the surface protective film
193
around the opening
192
is raised with respect to the other portion, so that the functional bump
194
has a projection height which is greater by &Dgr;h than the dummy bump
195
. With the functional bump
194
higher than the dummy bump
195
, the dummy bump
195
cannot properly be brought into contact with another semiconductor chip when the semiconductor chip is mounted on the another semiconductor chip. Therefore, the dummy bump fails to satisfactorily exhibit its function.
Where the dummy bump and the functional bump are formed in the same process step, there is a level difference, as shown in
FIG. 24
, between the surface of a surface protective film
291
and the surface of an internal interconnection
293
exposed through an opening
292
formed in the surface protective film
291
, so that the dummy bump denoted at
294
has a projection height which is greater by &Dgr;d than a projection height of the function
Hikita Junichi
Kumamoto Nobuhisa
Nakatani Goro
Sameshima Katsumi
Shibata Kazutaka
Rabin & Berdo P.C.
Vu Hung
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