Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-02-16
2004-03-16
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S777000, C257S737000, C257S691000, C257S698000, C257S723000, C257S665000, C257S728000, C257S784000
Reexamination Certificate
active
06707159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip which is applicable, for example, to a chip-on-chip structure in which semiconductor chips are bonded to each other in a stacked relation and to a flip-chip-bonded structure in which a semiconductor chip is bonded to a printed wiring board with its face opposed to the printed wiring board. The invention further relates to a production process for such a semiconductor chip.
2. Description of Related Art
For size reduction and higher integration of a semiconductor device, a so-called chip-on-chip structure has been proposed in which a pair of semiconductor chips are disposed in an opposed relation and electrically connected to each other via bumps.
Further, a wireless bonding technique has been used, by which electrodes provided on a device formation surface of a semiconductor chip are directly connected to electrodes on a wiring substrate such as of a carrier tape, and the electrodes on the wiring substrate are connected to a printed board or a ceramic board.
In either of the aforesaid techniques, it is necessary to provide electrode projections generally called “bumps” on the electrodes of the wiring substrate or on the device formation surface of the semiconductor chip.
On the other hand, a multiplicity of internal interconnections are provided in the device formation surface of the semiconductor chip to fulfill functions of the chip and, therefore, the chip should be designed so as not to complicate the routing of these interconnections.
However, there is a limit to the routing of the interconnections within the limited device formation surface, thereby hindering the size reduction and higher integration of the chip.
SUMMARY OF THE INVENTION
For implementation of a semiconductor device of chip-on-chip structure, the inventors of the present invention have come up with an idea that a surface interconnection composed of the same oxidation-resistant material as a bump is provided on a surface of each of opposed semiconductor chips. Where the surface interconnection is connected to the bump, for example, electrical connection between the opposed semiconductor chips can be achieved by bonding the surface interconnection of one of the semiconductor chips to the bump of the other semiconductor chip. This increases flexibility in layout of the bump on the other semiconductor chip. Further, an increased number of interconnections can be provided by connecting internal interconnections via the surface interconnection without increasing the thickness of the semiconductor chip.
Referring to
FIG. 13
, where surface interconnections
81
and
91
are respectively provided on opposed surfaces of semiconductor chips
80
and
90
, however, there is a possibility that the surface interconnections
81
,
91
of the semiconductor chips
80
,
90
are brought into contact with each other, resulting in unintended electrical connection between the semiconductor chips
80
and
90
.
Besides the chip-on-chip structure, the so-called flip-chip-bonded structure in which a semiconductor chip is bonded to a printed wiring board with their surfaces opposed to each other may also suffer from this problem when a surface interconnection is provided on the surface of the semiconductor chip.
In view of the foregoing, it is an object of the present invention to provide a semiconductor chip which is free from unintended electrical connection to the other semiconductor chip and features an increased flexibility in routing of interconnections with the use of a surface interconnection for size reduction and higher integration thereof, and to provide a production process for such a semiconductor chip.
The semiconductor chip according to the present invention comprises: a bump projecting from a surface protective film thereof for electrical connection between the semiconductor chip and another device; and a surface interconnection provided on the surface protective film and having a smaller height than the bump.
With this arrangement, the surface interconnection can be used in place of part of an internal interconnection in the chip, thereby simplifying the routing of internal interconnections. Further, the surface interconnection can have a lower resistance and a higher heat conductivity so as to carry a relatively large electric current. Thus, the surface interconnection can advantageously be used, for example, as a grounding line or as a power supply line.
The semiconductor chip may be bonded, for example, onto a surface of a solid body. In this case, the surface protective film covers a surface of the semiconductor chip which is opposed to the surface of the solid body, and the bump may serve for electrical connection to the solid body.
The surface of the solid body may be a surface of another semiconductor chip or a surface of a wiring board.
With this arrangement, the surface interconnection provided on the surface protective film has a smaller height than the bump projecting from the surface protective film. Therefore, there is no possibility that, when the semiconductor chip and the solid body (i.e., another semiconductor chip or the like) are bonded to each other in an opposed relation, the surface interconnection of the semiconductor chip is brought into contact with a surface interconnection and the like provided on the opposed surface of the solid body, thereby eliminating the possibility of unintended electrical connection between the semiconductor chip and the solid body via the surface interconnections.
The surface interconnection may project from the surface protective film or may be flush with the surface protective film.
The surface interconnection may be connected to the bump. For example, inter-bump interconnection can be achieved via the surface interconnection.
The bump may include a peripheral bump which is provided outside a device formation region of a semiconductor substrate which is a base of the semiconductor chip. In this case, the peripheral bump is preferably configured as surrounding the device formation region. More specifically, the peripheral bump may be provided in a scribe line region.
The surface interconnection may be connected to the peripheral bump. In this case, the peripheral bump is preferably to be connected to the ground or a power source.
The production process for the semiconductor chip in accordance with the present invention comprises the steps of: providing an internal interconnection on a semiconductor substrate; forming a surface protective film over the internal interconnection; forming an opening in the surface protective film to expose a portion (electrode) of the internal interconnection; forming a bump projecting from the surface protective film on the portion of the internal interconnection exposed through the opening; and forming a surface interconnection having a smaller height than the bump in a predetermined region on the surface protective film except a portion thereof formed with the opening.
By this process, the surface interconnection having a smaller height than the bump can be formed on the surface protective film.
The bump forming step may comprise the step of selectively depositing a conductive material on the portion of the internal interconnection exposed through the opening. The surface interconnection forming step may comprise the step of selectively depositing the conductive material in the predetermined region on the surface protective film except the portion thereof formed with the opening.
The formation of the bump and the surface interconnection may be achieved by selectively depositing the conductive material on the portion of the internal interconnection exposed through the opening and in the predetermined region on the surface protective film except the portion thereof formed with the opening to form a part of the bump and the surface interconnection, and further selectively depositing the conductive material on the part of the bump to complete the bump which projects from the surface protective film.
The process may further
Kumamoto Nobuhisa
Samejima Katsumi
Parekh Nitin
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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