Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-01-28
2003-01-14
Enad, Elvin (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S787000, C257S796000, C361S056000
Reexamination Certificate
active
06507117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip having a protective circuit prepared for an input of an abnormal voltage or current supplied from the outside due to static electricity or the like, and also to a multichip-type semiconductor device having semiconductor chips each of which has the arrangement of the semiconductor chip above-mentioned.
2. Description of Related Art
In a multichip-type semiconductor device in which a plurality of semiconductor chips are being resin-molded as connected to one another, the mutual connection of the semiconductor chips is conducted in any of a variety of manners. For example, there are instances where the semiconductor chips are connected to one another by bonding wires. There are also instances where the semiconductor chips are piled up on one another to form a chip-on-chip structure and are electrically connected to one another through bumps. There are also instances where the semiconductor chips are bonded onto a printed circuit board, thus achieving the mutual electrical connection of the semiconductor chips.
Each of the semiconductor chips forming a multichip-type semiconductor device, is provided on the surface thereof with a plurality of pads for electrical connection with another semiconductor chips. The pads are connected to an internal circuit formed on a semiconductor substrate serving as the base body of the semiconductor chip. The semiconductor chip itself can also be used as a single element. In such a case, pads are connected to lead frames which are pulled out to the outside of the package.
FIG. 6
is a block diagram illustrating an electric arrangement relating to a pad
101
of a semiconductor chip
100
. The pad
101
is connected to an internal circuit
103
through a wiring
102
. In the vicinity of the pad
101
, a diode
105
is connected to the wiring
102
between the same and the power line, while a diode
106
is connected to the wiring
102
between the same and the ground. These diodes
105
,
106
form a surge protective circuit
104
. This surge protective circuit
104
is arranged to absorb a surge entered through the pad
101
from the outside of the semiconductor chip
100
, thus preventing the internal circuit
103
from being damaged.
There are instances where an excessive voltage is externally applied to the semiconductor chip
100
. For example, an excessive voltage is applied when a functional test is conducted with a test probe applied to the pad
101
, before the semiconductor chip
100
is assembled into a multichip-type semiconductor device. Further, when the semiconductor chip
100
itself is used as a single element, there is a likelihood that an excessive voltage due to static electricity is applied to the pad
101
through a lead frame. In such a case, the surge protective circuit
104
is actuated to protect the internal circuit
103
.
However, the diodes
105
,
106
accompany large parasitic capacitances C
1
, C
2
. Accordingly, when it is particularly intended to operate the semiconductor chip
100
at high speed, the power consumption is disadvantageously increased due to charge and discharge of the parasitic capacitances C
1
, C
2
. Further, when the large parasitic capacitances C
1
, C
2
are connected to the wiring
102
, there are instances where restrictions are imposed on the operational speed, resulting in a failure to achieve an operation at the target speed.
A similar trouble is also caused by a large parasitic capacitance accompanying with a driver circuit connected to a signal output pad. More specifically, there is interposed, between the signal output pad and an internal circuit, a driver circuit for driving a volt-ammeter used when a functional test is conducted or for driving an external wiring when the semiconductor chip itself is used as a single element. This driver circuit is not necessarily required when connecting, to one another, semiconductor chips in which a high electric current is not required to flow. However, the driver circuit cannot be eliminated in view of the need of a functional test. Accordingly, when a multichip-type semiconductor device is formed, large parasitic capacitances accompanying with the driver circuit inevitably introduce problems such as an increase in power consumption at a high-speed operation and a limited operational speed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor chip and a multichip-type semiconductor device each of which is capable of reducing the power consumption and achieving a high-speed operation.
A semiconductor chip according to the present invention comprises: an internal circuit formed on a semiconductor substrate; a chip connection pad formed on the semiconductor substrate and used for interchip connection to another semiconductor chip; an other-service-than-interchip-connection pad formed on the semiconductor substrate and used for other service than interchip connection; and a switching circuit formed on the semiconductor substrate for selectively connecting, to the internal circuit, the chip connection pad or the other-service-than-interchip-connection pad.
The “interchip connection” generally refers to the mutual connection of semiconductor chips to be encapsulated in the same package.
The other-service-than-interchip-connection pad may be a pad to which a test probe is connected when conducting a functional test for checking the operation of the semiconductor chip.
The other-service-than-interchip-connection pad may be a pad to which connected is a lead frame pulled out to the outside of the package. The other-service-than-interchip-connection pad may also be a pad commonly used for a test and for connection to the outside of the package.
According to the present invention, there are disposed the chip connection pad used for interchip connection and the other-service-than-interchip-connection pad used for other service than interchip connection, and these pads are selectively connected to the internal circuit by the switching circuit.
Therefore, for example, a protective circuit for protecting the internal circuit is preferably disposed as connected to the other-service-than-interchip-connection pad. According to the arrangement above-mentioned, when conducting a functional test on the semiconductor chip or when it becomes necessary to connect the internal circuit to the outside through the lead frame, the internal circuit is connected to the other-service-than-interchip-connection pad by the switching circuit and the other-service-than-interchip-connection pad is used. This enables the internal circuit to be protected against an abnormal input from the outside. On the other hand, when this semiconductor chip is connected to another semiconductor chip, the switching circuit is operated to connect the internal circuit to the chip connection pad to which the protective circuit is not connected. Thus, the internal circuit is not influenced by the parasitic capacitance accompanying with the protective circuit. This reduces the power consumption and achieves a high-speed operation.
Preferably, the parasitic capacitance accompanying with the chip connection pad is smaller than that accompanying with the other-service-than-interchip-connection pad.
For example, when the protective circuit is connected to the other-service-than-interchip-connection pad and such a protective circuit is not connected to the chip connection pad as done in the arrangement above-mentioned, the parasitic capacitance accompanying with the other-service-than-interchip-connection pad is large, and the parasitic capacitance accompanying with the chip connection pad is much smaller.
For example, when the semiconductor chip incorporates a driver circuit for driving a volt-ammeter for a functional test or an external wiring (mainly, a wiring outside of the package) to be connected through the lead frame, and this driver circuit is connected to the other-service-than-interchip-connection pad, there is present a large parasitic capacitance acco
Hikita Junichi
Mochida Hiroo
Enad Elvin
Lee Kyung
Rohm & Co., Ltd.
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