Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-04-16
2004-01-27
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S203000, C257S208000, C257S786000
Reexamination Certificate
active
06683323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and particularly, but not limited to, a semiconductor chip having a semiconductor element and a TEG element for checking a characteristics of the semiconductor element. The present application is based on Japanese Patent Application No. 2001-121685, which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, semiconductor chips have had TEG (Test Element Group) elements arranged therein for measuring and checking the characteristics of semiconductor elements used in the circuits of the chips. This is described, for example, in Japanese Patent Application Laid-Open No. Heisei 9-275188, wherein the TEG elements enable the characteristics of semiconductor chips to be checked before and after completion of the chips, thus contributing to improvement of reliability of each semiconductor chip.
Such TEG elements and the electrode pads connected to the TEG elements for measuring the characteristics of semiconductor elements (hereinafter, referred to as TEG-measuring electrode pads) are provided in semiconductor chips. Therefore, the semiconductor chips tend to increase in area due to the TEG elements and TEG-measuring electrode pads formed therein, which is negative toward the flow of demands for a compactness of semiconductor chips.
Further, with higher performance of semiconductor integrated circuits, more check items of electrical characteristics are being required for improving reliability, year after year. Thus, more TEG elements need to be included in chips in correspondence with increasing check items of characteristics. On the other hand, the increased number of TEG elements directly leads to an increase in the area of the semiconductor chips, and thus reduces wafer area available for actual semiconductor elements, causing a problem that becomes a factor driving cost up.
The problems described above are caused by a large area of a semiconductor chip occupied by TEG elements and TEG-measuring electrode pads. Thus, some attempts have been done to alleviate the problem.
That is, as methods of reducing TEG element-occupied areas, there are known two methods; one method places TEG elements in a corner portion of a semiconductor chip wherein semiconductor elements and the assembly electrode pads connected to the semiconductor elements are not placed, and the other collectively places a plurality of TEG elements in a given region of a semiconductor chip as disclosed in Japanese Patent Application Laid-Open No. Heisei 9-275188 described above.
The above described methods have not only a limit to the very effect of reducing the TEG element-occupied areas, but also a problem that the degree of area reduction by the methods is not adequate for the current circumstances where extremely various and many TEG elements are used.
On the other hand, another method of reducing area occupied by TEG-measuring electrode pads is known from Japanese Patent Application Laid-Open No. Heisei 4-361546. This application provides a technique of pad arrangement for sharing electrode pads between TEG elements, enabling six electrode pads to be used for two TEG elements, and thus reducing two electrode pads, though one TEG element usually requires four electrode pads. However, this method imposes a constraint on the arrangement of TEG elements and electrode pads therefor, and further cannot adequately reduce area occupied by TEG-measuring electrode pads.
Japanese Patent Application Laid-Open No. 2000-58614 allows reduction of the area of TEG-measuring electrode pads by sharing TEG-measuring electrode pads between a plurality of TEG elements. However, in the technique of this application, a plurality of TEG elements are vertical stacked and a mechanism of electrical switching is required for making a connection between an electrode pad and a target TEG element, thus resulting in complicated circuit design for three dimensional structure and a decreased degree of flexibility in design.
SUMMARY OF THE INVENTION
One illustrative, non-limiting embodiment of a semiconductor device attaining a circuit function of the present invention comprises: a plurality of circuit elements which are used to attain the circuit function; at least one TEG element which is not used to attain the circuit function; and a plurality of bonding pads which are used to supply and receive signals to or from the circuit elements, at least one of the bonding pads being used in common for the TEG element to supply or receive a signal to or from said TEG element.
REFERENCES:
patent: 5923048 (1999-07-01), Inoue
patent: 2002/0149120 (2002-10-01), Sugiyama
patent: 4-361546 (1992-12-01), None
patent: 09275188 (1997-10-01), None
patent: 9-275188 (1997-10-01), None
patent: 09-275188 (1997-10-01), None
patent: 2000-58614 (2000-02-01), None
patent: 2000260947 (2000-09-01), None
patent: 2002353321 (2002-12-01), None
Flynn Nathan J.
Mandala Jr. Victor A.
McGinn & Gibb PLLC
NEC Electronics Corporation
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