Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Patent
1995-12-21
1998-08-04
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
257697, 257710, 437221, 72359, 723792, H01L 2312, H01L 2348
Patent
active
057898103
ABSTRACT:
A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperates with the polygonal base to establish a well bounded by the plurality of walls and the polygonal base. The walls terminate generally in a termination plane, and the well clears the chip when the cap is abuttingly mounted at the termination plane on the substrate at the chip locus.
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patent: 5455457 (1995-10-01), Kurokawa
Taylor Lyman, Metals Handbook, Apr. 1960, pp. 33-45.
Cadovius Richard W.
Gross Larry D.
Crane Sara W.
International Business Machines - Corporation
Ostrowski David
Soucar Steven J.
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