Semiconductor assemblies with reinforced peripheral regions

Details Semiconductor assemblies with reinforced peripheral regions Semiconductor assemblies with reinforced peripheral regions

1995-08-18

1998-07-07

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

257685, 257686, 257690, H01L 23495, H01L 2302, H01L 2348, H01L 2352

Patent

active

057773793

ABSTRACT:
A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.

REFERENCES:
patent: 4751482 (1988-06-01), Fukuta et al.
patent: 5148265 (1992-09-01), Khandros et al.
"Wire Bonding" by Erik N. Larson, pp. 368-393, Multichip Module Technologies and Alternatives: The Basics, Doane et al., eds. 1993 no month.

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