Semiconductor array with self-adjusted contacts

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257302, 257382, 257401, 257903, H01L 27108, H01L 2976

Patent

active

058641556

ABSTRACT:
A semiconductor array with self-adjusted contacts includes a substrate having a surface, at least two mutually spaced-apart doped regions extending in a first lateral direction on the surface, and insulated regions each being associated with a respective one of the doped regions and extending in the first lateral direction on the same side. Contact surfaces each extend in the first lateral direction above a respective one of the doped regions and at least partially above the insulated region associated with the one doped region. An insulating layer has contact holes each being formed therein above a respective one of the contact surfaces for receiving a self-adjusted contact. A method for producing a semiconductor array with self-adjusted contacts includes producing one of the contact surfaces with a first fragment being a part of the contact surface extending above the doped region and a second fragment being a part of the contact surface extending above the insulated region. The first fragment is produced with a non-photolithographic process avoiding edge location errors. The second fragment extends above the first fragment and therefore above the doped region by at least a length of a maximum edge location error, as long as no edge location errors occur.

REFERENCES:
patent: 4729969 (1988-03-01), Suda et al.
patent: 4877755 (1989-10-01), Rodder
patent: 5406103 (1995-04-01), Ogawa
patent: 5463236 (1995-10-01), Sakao
patent: 5486712 (1996-01-01), Arima
patent: 5530276 (1996-06-01), Iwasa
patent: 5561311 (1996-10-01), Hamamoto et al.
Motorola Technical Developments Publ. Vol. 12, April 1991 (See et al.) "An Alignment-Tolerant Contact Process Using Landing Pads).

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