Semiconductor array including a matrix of cells and a method...

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S173000, C365S189080, C365S230030

Reexamination Certificate

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07817466

ABSTRACT:
A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

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patent: 2004/102576 (2004-11-01), None
patent: 2006/066890 (2006-06-01), None
Fazan et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs,” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp. 99-102, 2002.
Hamamoto et al., “A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications,” Proceedings of the 2006 IEEE International Conference on Integrated Circuit Design and Technology, Aug. 14, 2006, 6 pages.

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