Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-06
2004-06-01
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000
Reexamination Certificate
active
06744100
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus that is provided with an internal circuit in the central portion of a semiconductor chip and a plurality of external connection terminals in the peripheral portion of the semiconductor chip, wherein a plurality of different voltage levels are provided to the plurality of external connection terminals, and further provided is an electrostatic discharge (ESD) protective circuit to prevent the semiconductor apparatus from being damaged by ESD.
BACKGROUND ART
FIG. 9
is a block diagram showing a conventional semiconductor apparatus provided with an ESD protective circuit.
An analog functional block
105
a
and a digital functional block
105
d
are formed in an internal circuit
105
formed on a semiconductor substrate. The analog functional block
105
a
and the digital functional block
105
d
are electrically connected to each other via an interface
111
. An analog voltage AVcc as a power supply voltage and an analog ground AGND are electrically connected to the analog functional block
105
a
. A digital voltage DVcc as a power supply voltage and a digital ground DGND are electrically connected to the digital functional block
105
d.
An analog pad
109
a
is electrically connected to the analog functional block
105
a
via the ESD protective circuit
107
a
. The analog power supply voltage AVcc and the analog ground AGND are electrically connected to the ESD protective circuit
107
a.
A digital pad
109
d
is electrically connected to the digital functional block
105
d
via the ESD protective circuit
107
d
. The digital power supply voltage DVcc and the digital ground DGND are electrically connected to the ESD protective circuit
107
d.
The ESD protective circuits
107
a
and
107
d
are composed of, for example, metal oxide semiconductor field effect transistors (MOSFETs) and diffusion resistors (for more details, refer to Japanese Laid-open Patent Applications 8-37299, 8-236637, 8-288404, and 9-186296).
FIG. 10
is a circuit diagram showing an equivalent circuit of the ESD protective circuit
107
a.
The ESD protective circuit
107
a
is configured by a protective diode D
1
formed by an N-channel type MOSFET, a protective diode D
2
formed by an N-channel type MOSFET, and a diffusion resistor R.
The diffusion resistor R is provided on the signal line between a MOSFET that is a portion of the analog functional block
105
a
and the analog pad
109
a
. The source of the protective diode D
1
is connected to the analog power supply voltage AVcc. The drain of the protective diode D
1
and the drain of the protective diode D
2
are connected to each other, and further connected to the signal line between a diffusion resistor
8
b
and the analog pad
109
a
. The gate electrode of the protective diode D
1
, the source of the protective diode D
2
, and the gate electrode of the protective diode D
2
are grounded.
As the components of large scale integrated circuits (LSIs) become smaller, lightly doped drain (LDD) type MOSFETS, of which the ability to withstand ESD voltage is lower than that of single drain structured MOSFETs, are used more often than ever. Accordingly, it is getting more difficult to form protective components of the ESD protective circuit with only MOSFETs.
Further, since the integration scale of LSIs is getting greater, it is possible to form many system blocks on a single chip wherein many digital functional blocks and many analog functional blocks are disposed. In the case of a semiconductor apparatus provided with multiple digital functional blocks and multiple analog functional blocks, it is necessary for each functional block to have its own power supply in order to protect each functional block from the noise on common signal lines, for example, and to reduce power consumption of the entire LSI by using and managing multiple power supply voltages. Most of the multiple power supply voltages are generated external to the LSI and provided to the LSI through separate terminals of the LSI.
Further, in the case of a system LSI having an analog functional block, an exclusive power supply system is often used for the analog functional block, which requires a small-sized ESD protective circuit. Accordingly, it becomes obvious that the ESD withstanding voltage of such a system LSI becomes low.
Further, as showed in
FIG. 9
, in the case of an LSI having multiple power supply systems, if a large current needs to flow through the analog pad
109
a
, the electrostatic energy cannot be discharged by the ESD protective circuit
107
a
since the analog power supply AVcc and the analog ground AGND do not have enough capacity to let the current flow. The electrostatic energy may also be discharged through the digital power supply DVcc and/or the digital ground DGND. Thus, the internal circuit including the interface
111
electrically connecting the analog functional block and the digital functional block are damaged by the ESD.
DISCLOSURE OF INVENTION
Accordingly, it is an object of the present invention to provide a novel and useful semiconductor apparatus having multiple power supply systems of which ESD withstanding voltage is improved.
To achieve the above object, a semiconductor apparatus formed on a semiconductor substrate having a first conductivity type, according to the present invention includes an internal circuit in the central portion of a semiconductor substrate, a plurality of external connection terminals formed in a first portion of said semiconductor substrate around said internal circuit, each external connection terminal being electrically connected to said internal circuit, wherein a plurality of power supplies correspondingly supply different voltage levels to the plurality of external connection terminals, and a plurality of outer ESD protective circuits formed in a second portion of said semiconductor substrate or a common well region in said semiconductor substrate, around said first portion of said semiconductor substrate, wherein each of said outer ESD protective circuits further comprises a first diffusion region electrically connected to one of the external connection terminals, a second diffusion region formed separately from said first diffusion region, said second diffusion region being electrically connected to a higher voltage line of a main power supply, and a third diffusion region formed separately from said first diffusion region, at a side of said first diffusion region opposite from said second diffusion region, said third diffusion region being electrically connected to a lower voltage line of said main power supply.
The above main power supply refers to, among the multiple power supply systems, the power supply that supplies power to the largest portion of the internal circuit.
According to the present invention, the outer ESD protective circuit connected to the higher voltage line and the lower voltage line of the main power supply are disposed in a peripheral portion that is closer to the edge of the semiconductor chip than the external connection terminals. If electrostatic voltage is introduced through the external connection terminal, the electro static voltage is discharged through the outer ESD protective circuit so as not to damage the internal circuit. Accordingly the ESD withstanding voltage of the semiconductor apparatus is improved.
Further, the ESD protective circuit of this structure can be manufactured by ordinary manufacturing processes of semiconductor apparatuses without adding any special process.
Furthermore, since the ESD protective circuit transfers the electrostatic energy when the electrostatic voltage exceeds the withstanding voltage between two diffusion regions instead of electrical switching, the outer ESD protective circuit does not work under normal operating conditions. That is, the addition of the outer ESD protective circuit does not affect the operation of the internal circuit.
Other objects, features, and advantages of the present invention will become mor
Ricoh & Company, Ltd.
Wilson Allan R.
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