Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-27
2003-07-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06591406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor apparatus and a semiconductor apparatus layout method. More particularly, the present invention relates to a semiconductor apparatus having a bypass capacitor and a layout method of a semiconductor apparatus having a bypass capacitor.
2. Description of the Related Art
A layout method using an automatic layout system is used in designing a semiconductor apparatus. Such a layout method is known in Japanese Laid Open Patent Application (JP-A-Heisei, 10-340959). In this known layout method, a hard macro is firstly arranged as shown in
FIG. 1
(S
101
). At this time, a hard macro library
403
including a circuit connection information
401
, a cell library
402
, a terminal of a hard macro, a wiring inhibition and an external shape is inputted to an automatic layout system.
After the arrangement of the hard macro (S
101
), power supply wiring (S
102
), an automatic arrangement of a cell (S
103
) based on the circuit connection information, a schematic wiring (S
104
) and a detailed wiring process (S
105
) are carried out to then complete the layout. Japanese Laid Open Patent Application (JP-A-Heisei, 10-340959) also discloses a layout method which after the arrangement of the hard macro (S
101
), removes the terminal and the wiring within the hard macro and then generates a hard macro terminal.
In addition, in a semiconductor apparatus, there may be a case that a bypass capacitor is mounted between a power supply line and a ground line in order to suppress a noise. In this case, the bypass capacitor is manually arranged after the automatic layout. Thus, enormous labor is necessary for the arrangement of the bypass capacitor.
It is desirable to develop a method for arranging the bypass capacitor without requiring the enormous labor.
Also, a semiconductor apparatus having a bypass capacitor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-284605). This known semiconductor apparatus having the bypass capacitor is provided with cell rows
101
a,
101
b
and
101
c,
as shown in FIG.
2
. The cell rows
101
a,
101
b
include a feed through cell
102
. The feed through cell
102
is also referred to as a width alignment cell. Its role is to align the widths of the cell rows
101
a,
101
b
and
101
c
. Also, the feed through cell
102
is designed such that a wiring area can be reserved.
FIG. 3
shows a structure of the feed through cell
102
. In
FIG. 3
,
103
denotes a silicon substrate.
104
denotes an inter-layer film formed on the silicon substrate
103
.
105
denotes a first electrode formed on the inter-layer film
104
.
106
denotes a second electrode which is formed on its dielectric film
107
so as to be located opposite to the first electrode
105
and constitutes a capacitance together with the first electrode
105
and the dielectric film
107
.
108
denotes a first insulation oxide film formed on the second electrode
106
.
109
denotes a second insulation oxide film formed on the first insulation oxide film
108
.
110
denotes a power source wiring connected to the second electrode
106
through a contact hole
111
by using a first layer wiring. And,
112
denotes a ground wiring connected to the first electrode
105
through a contact hole
113
by using the first layer wiring.
The known semiconductor apparatus having the bypass capacitor uses the space between the first electrode
105
and the second electrode
106
as capacitance. The semiconductor apparatus is desirable which has the bypass capacitor in which the space is effectively used. At this time, it is further desirable that the bypass capacitor mounted in the semiconductor apparatus can have a structure for making an automatic design easy.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-283615) discloses a power supply wiring of a semiconductor integrated circuit as described below. In order to effectively reduce a noise induced in a power supply of LSI, in the LSI having a Vcc power supply/GND wiring with two or more layers and two or more rows, one Vcc power supply wiring is arranged in an upper layer, and a GND wiring is arranged in a lower layer. In rows adjacent to each other, a Vcc power supply wiring is arranged in a lower layer, and a GND wiring is arranged in an upper layer.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-204766) discloses a method for designing a semiconductor integrated circuit as described below. This is a method for designing a semiconductor integrated circuit including a plurality of basic cells, a power supply line and a ground line placed over those basic cells, and a plurality of bypass capacitors electrically connected to the power supply line and the ground line. This carries out the layouts of the plurality of basic cells, the power supply line and the ground line, and after tentatively setting the sizes of the respective bypass capacitors and the arrangement intervals of the bypass capacitors, respectively places the respective bypass capacitors, in which the sizes and the arrangement intervals are tentatively set, in empty areas of the basic cells in accordance with the layout, and if obtaining the desirable arrangement of the bypass capacitors, determines its arrangement as the final arrangement, and on the other hand, if failing in the desirable arrangement of the bypass capacitors, repeats the procedure for again setting the sizes of the bypass capacitors and the arrangement intervals between them and again placing the respective bypass capacitors until obtaining the desirable arrangement of the bypass capacitors.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-233636) discloses a semiconductor integrated circuit as described below. A macro cell, which has a pad portion that is placed in an area around a chip and is intended to input and output a signal from or to an external portion of the chip, and a function area mounted in an entirely inner area of the chip except the pad portion and is configured so as to have at least a desirable function in advance, and an input/output buffer for sending to the function area a signal inputted to or outputted from the external portion of the chip through the pad portion are placed at any position within the function area.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor apparatus including a bypass capacitor having a structure that makes automatic design easy. Another object of the present invention is to provide a semiconductor apparatus having a bypass capacitor in which space is effectively used. Still another object of the present invention is to provide a layout method that can make a layout of a semiconductor apparatus having a bypass capacitor easy.
In order to achieve an aspect of the present invention, a semiconductor apparatus, includes: a semiconductor substrate; a first wiring provided in the semiconductor substrate; a second wiring provided in the semiconductor substrate; and a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.
In this case, the capacitance cell is provided to overlap with the first and second wirings.
In order to achieve another aspect of the present invention, a semiconductor apparatus, includes: a semiconductor substrate; a function region provided in the semiconductor substrate, a predetermined function being performed in the function region; a first wiring provided in the semiconductor substrate; and a second wiring provided in the semiconductor substrate, and wherein the function region includes: a circuit cell having a circuit; and a capacitance cell, and wherein the capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring and the capacitance cell is arranged in a region where the circuit cell does not exist.
In this case, the capacitance cell occupies an entire portion other than the circuit cell
Dimyan Magid
NEC Electronics Corporation
Smith Matthew
Young & Thompson
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