Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold
Patent
1996-09-20
1998-11-24
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
257491, 257495, 257593, H01L 2358, H01L 27082
Patent
active
058411810
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to semiconductor apparatus such as diodes, transistors, thyristors, insulated-gate bipolar transistors (IGBTs), MOSFETs and ICs, particularly those which are improved in the breakdown voltage.
BACKGROUND ART
A conventional method for increasing the dielectric breakdown strength of semiconductor apparatus such as a transistor is shown schematically in FIG. 4. A base region indicated by 2 has a field-limiting ring (FLR) 4 provided external to its perimeter such that a depletion layer 11 formed below the pn junction 10 between the base region 2 and a collector region 1 is extended beyond the perimeter of the FLR 4.
The conventional transistor comprises the collector region 1 which comprises an n.sup.+ type semiconductor substrate 1a and an n.sup.- type semiconductor layer 1b of low impurity level that is formed on the substrate 1a by epitaxial growth, the p-type base region 2 which is formed in the collector region 1 by a suitable technique such as diffusion, and an emitter region 3 which is formed from an n.sup.+ type impurity in the base region 2 by a suitable technique such as diffusion. The FLR 4 which is of the same conduction type (p-type) as the base region 2 is provided external to the perimeter of the pn junction 10 between the base and collector regions. The transistor also has an insulator film typically formed of SiO.sub.2 and which is provided on the surface of the semiconductor layer 1b, a device defining annular member 6, a collector electrode 7, a base electrode 8, and an emitter electrode 9.
The transistor of the planar type described in the above is incapable of exhibiting the theoretical dielectric breakdown strength because charges and other impurities will be generated either within the oxide or otherwise formed insulator film 5 or at the interface between the semiconductor layer 1b and the insulator film 5. To deal with this problem and secure a higher breakdown voltage, the transistor uses a wafer having a higher specific resistance than the theoretical or FLR 4 is provided as shown in FIG. 4 such that the depletion layer 11 below the pn junction 10 between the base and collector regions is allowed to extend beyond the perimeter of the FLR 4. Having the same conduction type as the base region 2, FLR 4 is usually formed in the same step as the base region 2 and in a similar manner.
As shown in FIG. 5, the formation of the base region 2 by thermal diffusion is conducted simultaneously with the provision of a mask pattern for the making of the emitter region by forming an oxide film 51 on the surface of the semiconductor layer 1b, as well as oxide films 52 and 54 on the base region 2 and FLR 4, respectively, by a suitable oxidation technique such as thermal oxidation. During the oxidation, oxide films 52 and 54 grow rapidly since the base region 2 and FLR 4 have higher impurity levels than the n.sup.- type semiconductor layer 1b. On the other hand, the growth of oxide film 51 is slow because the n.sup.- type semiconductor layer 1b not only has a lower impurity level but also is overlaid with the oxide film 5. As the oxide films 51, 52 and 54 grow, the interface 62 between the semiconductor layer 1b and the oxide film 5 will move into the interior of the semiconductor layer 1b; however, due to the growth rate difference mentioned above, the interface 62 is shallow in the oxide film 51 and deep in the base region 2 and FLR 4. As a result, the interface 62 provides a discontinuous profile along the surface of the semiconductor layer 1b. At the same time, the n-type impurity in the semiconductor layer 1b and the oxide film 5, as well as the p-type impurity in the base region 2, FLR 4 and oxide films 52 and 54 will be redistributed through the interface 62 until the chemical potential is equilibrated on both sides of the interface. Because of this generally known effect, the impurities will be redistributed in the respective oxide films. The phenomena just described above occur again during the formation of the emitter region.
If the interface b
REFERENCES:
patent: B520115 (1976-03-01), Matsushita et al.
patent: 4158206 (1979-06-01), Neilson
Fahmy Wael
Rohm & Co., Ltd.
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