Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-28
2001-05-15
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S640000
Reexamination Certificate
active
06232641
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus and a manufacturing method therefor, and more particularly to a semiconductor apparatus incorporating a MOS transistor which has a structure in which a source region and a drain region are elevated over the original surface of the silicon substrate and a manufacturing method therefor.
In an industrial field of the MOS type integrated circuit, a SALICIDE (Self Aligned Silicide) technique has been developed to realize a precise and high-speed device. The SALICIDE technique is arranged to form a metal silicide film, such as a Co silicide film or a Ti silicide film, on a source diffusion layer and a drain diffusion layer, the metal silicide film being formed in a self-aligning manner.
As the degree of precision of the structure is enhanced, there arises a necessity of forming the source diffusion layer and the drain diffusion layer in a shallower position from the surface of the substrate.
When the foregoing SALICIDE technique is employed to manufacture a precise device, silicide forming reactions between a metal film having a high melting point and the silicon substrate proceed while the metal film having a high melting point consumes silicon of the silicon substrate. Therefore, joint between a well and the source region or the well and the drain region cannot easily be formed in a shallow region from the surface of the substrate.
To solve the above-mentioned problem, epitaxial silicon films are formed on the surfaces of the source region and the drain region on the surface of the silicon substrate. Thus, the surfaces of the source region and the drain region are elevated over the original surface of the silicon substrate.
Then, ions of impurities are implanted into the surface of the substrate through the epitaxial silicon film, and then the metal film having a high melting point is deposited to perform the silicide forming reactions. Thus, the source region and the drain region each having low resistance are formed. Simultaneously, joints are formed in a shallow region from the surface of the substrate.
The foregoing technique for epitaxial-growing silicon on the source region and the drain region to elevate the surfaces of the source region and the drain region over the original surface of the silicon substrate is called an “elevated source and drain technique”.
The structure in which the source region and the drain region are elevated over the original surface of the substrate is hereinafter called an “elevated source and drain structure”.
FIG. 1
is cross sectional view showing a MOS transistor having the conventional elevated source and drain structure.
A gate electrode
83
made of polysilicon is formed on a silicon substrate
81
through a gate oxide film
82
. A gate-side-wall SiN film
85
made of silicon nitride (SiN) is formed on the side wall of the gate electrode
83
through a SiO
2
liner
84
.
A source diffusion layer
86
and a drain diffusion layer
87
are formed on the surface of the silicon substrate
81
in a self-aligning manner. A source silicon film
88
and a drain silicon film
89
, each of which is made of single crystal silicon, are, by the epitaxial growth method, formed on the source diffusion layer
86
and the drain diffusion layer
87
, respectively.
The MOS transistor of the type having the elevated source and drain structure, however, suffers from the following problems.
That is, the elevated source film
88
and the elevated drain film
89
are, however, caused to have facets
90
formed adjacent to the lower ends of the gate-side-wall SiN film
85
. Therefore, the degree of elevation of the source region and the drain region is undesirably restrained.
As a result, a problem arises when ions of impurities are implanted into the surface of the substrate through the elevated source film
88
and the elevated drain film
89
to form the source diffusion layer
86
and the drain diffusion layer
97
. That is, the regions of the source diffusion layer
86
and the drain diffusion layer
87
, in each of which satisfactory elevation cannot be realized, are undesirably formed deeply. Moreover, the concentration of the impurities is raised excessively.
As a result, electric fields produced in channel regions during the operation of the transistor form a depletion layer in the channel region. Thus, |V
th
| (an absolute value of a threshold voltage) is lowered and durability between the source and the drain deteriorates. That is, a problem of a short-channel effect arises.
Since the portions encountered the facet inhibits formation of the joints in a shallow region from the surface of the substrate, a joint leak current is produced which causes the characteristics of the transistor to excessively deteriorate.
When the SALICIDE technique is employed to manufacture a precise MOS transistor, silicide forming reactions proceed while the metal film having a high melting point consumes silicon of the silicon substrate. Therefore, a shallow joint cannot easily be formed.
Therefore, a MOS transistor of a type having the elevated source and drain structure has been suggested. That is, the following method has been suggested in which the epitaxial silicon films are formed on the source region and the drain region to elevate the surfaces of the source region and the drain region over the original surface of the substrate. Then, implantation of ions of impurities and the silicide reactions are performed. Thus, the source diffusion layer and the drain diffusion layer each of which has low resistance and which are joined at shallow positions are formed.
The epitaxial silicon film, however, encounters formation of a facet adjacent to the lower ends of the gate edges. As a result, the source region and the drain region cannot satisfactorily be elevated in the portions encountered the formation of the facets.
As a result, the deep source diffusion layer and drain diffusion layer in the portions in which satisfactory elevation has been inhibited are formed deeply and caused to contain impurities in high concentrations. Therefore, there arises a problem in that the short-channel effect occurs. What is worse, a shallow joint cannot be formed in the portion encountered formation of the facet. As a result, there arises another problem in that a joint leak current is produced.
BRIEF SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor apparatus on which a MOS transistor is formed which has an elevated source and drain structure to prevent a short-channel effect and a joint leak current, and a manufacturing method therefor.
To achieve the object, according to one aspect of the present invention, there is provided a semi-conductor apparatus on which a MOS transistor having an elevated source and drain structure is formed, comprising:
a silicon substrate;
a gate electrode formed on the surface of the silicon substrate through an insulating film;
an elevated source film and an elevated drain film formed in a source region and a drain region of the surface of the silicon substrate and each having at least a surface made of a metal silicide film and conductivity such that the elevated source film and the elevated drain film are elevated over the surface of the silicon substrate and the MOS transistor having a structure that the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate owning to the formation of the elevated source film and the elevated drain film;
a first gate-side-wall insulating film formed on the side wall of a gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate; and
a second gate-side-wall insulating film formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film, made of a material which can be etched at an etching rate lower than that permitted for a material of the first gate-side-wall insulati
Miyano Kiyotaka
Mizushima Ichiro
Saito Tomohiro
Tsunashima Yoshitaka
Crane Sara
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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