Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-13
2004-02-17
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S312000
Reexamination Certificate
active
06693316
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor apparatus having a charge pump circuit, and more particularly to a semiconductor apparatus having a charge pump circuit which includes MOS type charge pump capacitors.
BACKGROUND OF THE INVENTION
Semiconductor apparatuses such as an LCD driver which has a low-voltage logic and a high-voltage logic on the same semiconductor chip are designed to generate a high voltage by stepping up a low-voltage of a low voltage supply using a charge pump circuit.
FIG. 1
illustrates such a charge pump circuit
11
, in which a high voltage Vo (15 V) is obtained for a load
12
by stepping up a low voltage supply Vcc (about 3 V) of the power supply
13
. As shown in
FIG. 1
, the charge pump circuit
11
has: p-type MOSFETs Q
1
-Qn connected in series between an input terminal IN and an output terminal OUT; series inversion buffer circuits B
1
-Bn for supplying gate voltages to the respective MOSFETs Q
1
-Qn; capacitors C
1
-Cn each having one end connected with a respective MOSFET (Q
1
-Qn) or with the output terminal OUT; series inversion buffer circuits B
1
a
-Bn-
1
a
for supplying, predetermined voltages to the respective capacitors Q
1
-Qn; inversion buffer circuits B
1
-Bn; and an oscillator circuit OSC for providing clock signals to the inversion buffer circuits B
1
a
-Bn-
1
a
, the clock signals switching between predetermined high and low levels. (Capacitors C
3
through Cn-1 and inversion buffer circuits B
3
through Bn-
1
a
are not shown.) The capacitor Cn in the last stage may be external to the charge pump circuit as shown in
FIG. 1
, if necessary, when large power is required by the load.
In operation, the charge pump circuit
11
generates a low (L) output at the output of the inversion buffer circuit B
1
to thereby turn on the MOSFET Q
1
when the output of the oscillator circuit OSC is high (H), and causing the output of the inversion buffer circuit B
2
to become H to thereby turn off the MOSFET Q
2
. The outputs of the inversion buffer circuit B
1
a and the B
2
a are L and H, respectively. Consequently, the capacitor C
1
is charged to the supply voltage Vcc.
Next, as the output of the oscillator circuit OSC goes low L, the output of the inversion buffer circuit B
1
goes high H, thereby turning off the MOSFET Q
1
, while the output of the inversion buffer circuit B
2
goes low L, thereby turning on the MOSFET Q
2
. At this stage, the output levels of the inversion buffer circuits B
1
a
and B
2
a
are H and L, respectively. Consequently, as a result of charge conservation principle, the capacitor C
2
is charged with the charged voltage (Vcc) of the capacitor C
1
plus the high output (Vcc) of the inversion buffer circuit B
1
a, thereby creating two times the supply voltage Vcc across the capacitor C
2
.
In this way, at every inversion of the oscillator circuit OSC between H and L levels, capacitor Cn acquires a voltage stepping up towards the required voltage Vo for the load
12
.
Thus, in forming a charge pump circuit on one semiconductor chip together with a low-voltage circuit (not shown), their capacitors C
1
-Cn-
1
are mostly MOS capacitors, aligned in shape and size with other MOS transistors.
Such MOS capacitors are described in detail below with reference to
FIGS. 2 and 3
. An N-well region
21
is formed on a p-type semiconductor substrate (referred to as substrate)
20
. Formed within the N-well region
21
are N
+
regions
22
-
1
and
22
-
2
which are enriched with impurity to provide a higher conductivity. Formed on an insulating oxide layer (not shown) which overlies the N-well region
21
, and between the N
+
regions
22
-
1
and
22
-
2
, is a gate electrode
23
. If a p-type MOSFET were formed on the N-well region
21
, the N
+
regions
22
-
1
and
22
-
2
would make a p
+
-type drain and a source, respectively, and the N-well region
21
between the N
+
regions
22
-
1
and
22
-
2
, a channel region. (The N-well region will be hereinafter sometimes referred to channel region.)
A gate electrode
23
is connected with a lead wire
24
(which is an aluminum wiring layer
26
in
FIG. 3
) for connection with the terminal T
1
. The N
+
regions
22
-
1
and
22
-
2
are connected with a common lead wire
25
(which is an aluminum wiring layer
27
in
FIG. 3
) to maintain the regions at the same potential and to connect the regions with the terminal T
2
. Thus, a capacitor is provided between the gate electrode
23
and the N
+
regions
22
-
1
and
22
-
2
, serving as a MOS capacitor. Similar capacitors are formed between the two wiring layers
26
and
27
and between the wiring layer
27
and the gate electrode
23
, however, their capacitances are not important. In addition, oxide layers
28
-
1
and
28
-
2
are provided on the opposite ends of the N-well for isolation thereof from adjacent N-wells.
The magnitudes of these capacitances may not be sufficient for building up the required charging voltage when the power consumed by the load
12
is large. In that case, in order to provide sufficiently large power at all times, the switching frequency of the MOSFETs Q
1
-Qn, i.e., the frequency of the oscillator circuit OSC, must be set high.
Unfortunately, the MOS capacitors as shown in
FIGS. 2 and 3
have a disadvantageous characteristic (hereinafter referred to as voltage dependent characteristic) that their capacitances vary with the voltages applied thereto. This is because the capacitance of the MOS capacitor is determined by the sum of two series capacitances, that is, the capacitance of the dielectric gate oxide layer and the capacitance of the channel region (e.g. capacitance of the depletion layer) which depends on the physical condition of the channel region.
Although the capacitance of the gate oxide layer depends on the thickness thereof, it has a fixed value in that it has no voltage dependence. The capacitance of the channel region, on the other hand, depends on the physical conditions of the channel region, which in turn depends on the voltage applied thereto in different ways. For example, it depends on whether the channel is formed or not, and the thickness of the channel formed. Thus, the MOS capacitance depends on the voltage.
Of course the voltage dependence of the MOS capacitor would not matter so long as the capacitor can build up a sufficiently large voltage. However, a MOS capacitor for a charge pump circuit is subjected to frequent charging and discharging, and hence its voltage is always changing. Particularly, the voltage impressed on the first stage MOS capacitor is low and the resistance of the N-well region
21
forming the channel is large, so that it requires a fairly long time to gain an appreciable capacitance subsequent to the application of the voltage, thereby exhibiting a poor frequency response.
FIG. 4
shows such voltage dependent characteristic of the MOS capacitor for a switching frequency SW.f of 1 MHz. In
FIG. 4
, the abscissa represents the voltage Vg across the terminals T
1
and T
2
of a MOS capacitor. The ordinate represents the capacitance C of the MOS capacitor. The voltage Vg is applied across the terminals T
1
and T
2
, with the terminal T
1
being positive.
The static saturation capacitance of the MOS capacitor is about 750 pF as shown by a dotted line in FIG.
4
. It is seen that the voltage dependence is saturated in the range from 2 V to 3 V. However, the rise of the capacitance is not steep and its saturated level is lower than the static capacitance due to high switching frequency. This characteristic varies with switching frequency.
The frequency response of the MOS capacitor may be improved through an additional manufacturing step of minimizing the resistance of the electrodes and modifying the characteristics of the N-well.
It is, however, not quite as easy to change the resistance of the electrodes and the characteristic of the N-well because the MOS capacitors are formed in the process of manufacturing the MOSFETs. Besides, if the change were possible, it would require additional t
Oku Hironori
Tanaka Toshimasa
Hogan & Hartson
Rohm & Co., Ltd.
Rose Kiesha
Zarabian Amir
LandOfFree
Semiconductor apparatus having a charge pump circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor apparatus having a charge pump circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor apparatus having a charge pump circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3287136