Semiconductor apparatus design method in which dummy line is...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C438S622000, C438S691000

Reexamination Certificate

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07665055

ABSTRACT:
A design method places a dummy line in floating state in a line layer of a semiconductor apparatus by using a computer. The method includes a first step of reading layout data and placing a dummy line with a longitudinal side lying in parallel with a signal line in an area where a pattern density of the signal line in a prescribed area is equal to or lower than a density lower limit, and a second step of dividing a dummy line placed in an area where a distance from the signal line is equal to or shorter than a dummy dividing distance.

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Kahng et al.;“Study of floating fill impact on interconnect capacitance”; Quality Electronic Design; ISQED '06; 7th International Symposium on Mar. 27-29, 2006 pp. 691-696.

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