Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-09
2001-03-20
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S387000, C257S401000, C257S412000, C257S751000, C257S754000, C438S289000, C438S655000, C438S694000
Reexamination Certificate
active
06204539
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus and a manufacturing method therefor, and more particularly to the structure of a MISFET having a silicide compound of metal of a type having a high melting point in order to lower parasitic resistance and a method of forming the MISFET, which is used to manufacture, for example, a semiconductor memory.
To raise the density of integration of LSI devices and improve the performance of the same, devices such as MISFET have been formed more precisely. The above-mentioned trend of precisely forming the devices encounters adverse influences of resistance components which are parasitic on the MISFET.
To reduce the resistance which is parasitic on the MISFET device, silicide compounds of metal, such as Ti, Co, Ni and Pt, having a high melting point are formed on a gate electrode of the MISFET and an impurity-diffused layer (source and drain diffusion layer) for the drain and source of the same. Thus, reduction in the resistance components of the gate electrode, the impurity diffused layer for the source and drain and their contact portions has been attempted.
The conventional method of forming the MISFET has the step of forming a contact hole in an interlayer insulating film to form the contact portion of the source and drain diffusion layer. The insulating film on the side wall of the gate electrode which is used when the silicide compound is formed interrupts etching, causing the area of opening of the contact hole to be reduced. Hence it follows that the resistance of the contact portion is raised, causing a problem to arise in that the performance of the MISFET deteriorates.
When a contact hole is formed in a portion which is not interrupted by the insulating film on the side wall of the gate electrode, the distance (the contact distance) from the gate electrode to the contact portion of the source and drain diffusion layer is elongated. Thus, the parasitic resistance of the drain and source portion is raised, causing a problem to arise in that the performance of the MISFET deteriorates.
A process for forming the MISFET having the conventional salicide (Self Aligned Silicide) structure will now be described with reference to
FIGS. 4A-4J
such that an nMISFET is taken as an example.
As shown in
FIG. 4A
, a heat oxide film (an SiO
2
)
102
having a thickness of, for example, 10 nm is formed on a p-type Si substrate
101
by heat oxidation. Then, polycrystal Si film
103
having a thickness of 200 nm is formed on the SiO
2
film
102
by an LP (Low Pressure)-CVD (Chemical Vapor Deposition) method. Then, an SiO
2
film
104
having a thickness of 200 nm is formed on the polycrystal Si film
103
by the LP-CVD method. Then, a photoengraving method is employed to form a resist pattern
105
on a region in which a device will be formed.
Then, as shown in
FIG. 4B
, the resist pattern
105
is used as a mask to perform anisotropic dry etching capable of realizing a selection ratio with respect to the polycrystal Si film
103
. Thus, the SiO
2
film
104
is etched so that the resist pattern
105
is peeled such that the region of the SiO
2
film
106
is left.
Then, an SiO
2
film
106
is used as a mask to perform anisotropic dry etching capable of realizing a sufficiently high selection ratio with respect to the SiO
2
film
102
to etch the polycrystal Si film
103
. Thus, the region of a polycrystal Si film
107
is left. Then, the SiO
2
film
102
is etched so that the region of an SiO
2
film
108
is left.
Then, as shown in
FIG. 4C
, anisotropic dry etching capable of realizing a sufficiently high selection ratio with respect to the SiO
2
film
106
is performed to etch the p-type Si substrate
101
by 0.5 &mgr;m. Thus, a STI (Shallow Trench Isolation) groove
109
is formed.
Then, as shown in
FIG. 4D
, the LP-CVD method is employed to deposit an SiO
2
film
110
having a thickness of 1.5 &mgr;m on the overall surface. Then, a CMP (Chemical Mechanical Polishing) method capable of realizing a sufficiently high selection ratio with respect to the polycrystal Si film
107
is employed to flatten the SiO
2
film
110
.
Then, NH
4
F or dry etching is employed to etch the SiO
2
film
106
and the SiO
2
film
110
until the polycrystal Si film
107
is just exposed so that the embedded SiO
2
film
110
is left.
Then, as shown in
FIG. 4E
, isotropic dry etching capable of realizing a selection ratio with respect to the SiO
2
film
108
is performed to remove the polycrystal Si film
107
by etching. Then, the film stress of the embedded SiO
2
film
110
is reduced by performing heat treatment at, for example, 1000° C.
Then, the SiO
2
film
108
on the surface of the p-type Si substrate
101
is removed by etching using NH
4
F, and then heat oxidation is performed at, for example, 800° C. so that an SiO
2
film (a sacrifice oxide film)
111
is formed.
Then, a p-well region
112
is formed by implanting B (boron) ions under conditions that accelerating voltage is 200 KeV and a quantity of dose is 8×10
12
cm
−2
. To control the threshold of the nMISFET, boron ions are implanted under conditions that, for example, the accelerating voltage is 50 KeV and a quantity of dose is 1×10
13
cm
−2
. To activate introduced impurities, heat treatment is performed at a predetermined temperature and duration.
Then, the SiO
2
film (the sacrifice oxide film)
111
on the surface of the p-type Si substrate
101
is removed, and then heat oxidation is performed at 750° C. so that a gate insulating film
113
having a thickness of 6 nm is formed, as shown in FIG.
4
F.
Then, a gate electrode
116
is formed by depositing polycrystal Si by the LP-CVD method by a thickness of 300 nm. Then, the photograving method is employed to form a resist pattern
115
for forming a gate electrode. Anisotropic dry etching capable of realizing a sufficiently high selection ratio with respect to the SiO
2
film
110
is performed to etch the polycrystal Si film (the gate electrode
116
is left).
Then, as shown in
FIG. 4G
, a shallow diffusion layer (a shallow extension)
117
which will be formed into the source and drain layer of the nMISFET is formed by performing heat oxidation at 800° C. to form an SiO
2
film (a post-oxidation film) having a thickness of, for example, 5 nm. Then, implantation of As ions is performed under conditions that accelerating voltage is 35 KeV and a quantity of dose is 2×10
14
cm
−2
. Then, heat treatment is performed for 30 seconds in a N
2
atmosphere at 1000° C.
Then, as shown in
FIG. 4H
, a deep diffusion layer (a deep extension)
119
which will be formed into the source and drain diffusion layer of the nMISFET is formed by, initially, forming an insulating film
118
on the side wall of the gate (a SiN side wall portion) made of, for example, SiN. At this time, the LP-CVD method is employed to deposit SiN on the overall surface by a thickness of 150 nm. Then, anisotropic etching capable of an etching selection ratio with respect to the SiO
2
film (the post-oxidation film) is performed to etch the SiN film (the insulating film
118
on the side wall of the gate is left).
Then, for example, As ions are implanted under conditions that the accelerating voltage is 60 KeV and a quantity of dose is 5×10
15
cm
−2
. Then, heat treatment is performed for 30 seconds in a N
2
atmosphere at 1000° C. so that a deep diffusion layer
119
is obtained. Moreover, the gate electrode
116
is doped into an n+ type.
Then, the SiO
2
film on the gate electrode
116
of the nMISFET and the SiO
2
(
113
) on the deep diffusion layer
119
which will be formed into the source and drain diffusion layer are removed by using NH
4
F.
To form, for example, a Ti salicide structure, Ti (titanium)/TiN (titanium nitride), which are metal materials each having a high melting point, are deposited by 30 nm/20 nm. Then, heat treatment is performed for 30 second in a N
2
atmosphere at 700° C. Mixed solution of sulfuric acid and hydrogen peroxide solution is used to re
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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