Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Utility Patent
1998-05-14
2001-01-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S635000, C438S648000, C438S656000, C438S682000, C438S685000, C257S758000, C257S764000, C257S768000
Utility Patent
active
06169019
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus having a self-alignment contact structure and a manufacturing method therefor.
The performance of an integrated circuit apparatus can be improved and a degree of integration can be raised by reducing the size of each of devices for forming the integrated circuit.
In a case of a MOS transistor, the degree of integration can be raised by reducing the width of a gate electrode, a contact diameter of a contact hole with respect to a source/drain diffusion layer and a width (hereinafter called a “aligning margin”) between the contact hole and a device isolation film if an assumption is made that the mask is not displaced.
The aligning margin d between a contact hole
10
and a device isolation film
11
exerts a considerable influence on an attempt to raise the degree of integration, as shown in FIG.
19
. On the other hand,. the aligning margin d does not exert a considerable influence on the performance of the transistor. That is, the aligning margin d does not deteriorate the performance of the transistor. Therefore, reduction of the aligning margin d is an effective means to improve the degree of integration.
However, if the displacement in alignment between the pattern of the contact hole of the reticle and the pattern of the transistor of the integrated circuit apparatus is greater than the aligning margin d when lithography of a photoresist is performed to determine the position of the contact hole
10
with respect to a source/drain diffusion layer
12
, there arises a problem in that leakage currents are enlarged.
The foregoing problem will now be described.
If the displacement in alignment is greater than the aligning margin d, a portion of the contact hole
10
overlaps the device isolation film
11
, as shown in FIG.
20
.
Both of the device isolation film
11
and the interlayered insulating film of a usual integrated circuit apparatus are made of oxide films (SiO
2
) or the like because of an excellent insulating characteristic and a low dielectric constant of the oxide film.
That is, the device isolation film
11
and the interlayered insulating film are made of the same material. Therefore, a low etching selection ratio is realized between the device isolation film
11
and the interlayered insulating film. Thus, when a photoresist pattern mask is used after a lithography process has been performed to etch a interlayered insulating film
14
by a RIE method or the like, a portion of the device isolation film
11
(a LOCOS film or a STI (Shallow Trench Isolation) film) overlapping the contact hole
10
is undesirably etched.
Above-mentioned overetching is caused from the structure that the device isolation film
11
and the interlayered insulating film
14
are made of materials of the same system (that is, materials having a low etching selection ratio).
If the device isolation film
11
is etched, the distance from a pn junction surface between the silicon substrate
16
and the source/drain diffusion layer
12
to the interface between the metal layer
15
and the source/drain diffusion layer
12
in the contact hole
10
is undesirably shortened, as shown in FIG.
21
. In the worst case, the metal layer
15
and the silicon substrate
16
are short-circuited, as shown in FIG.
22
. In this case, electric charges are introduced from the metal layer
15
into the silicon substrate
16
, causing leakage currents to easily flow.
A method which is capable of preventing the above-mentioned problem has been known with which a film having a large etching selection ratio with respect to the interlayered insulating film and the device isolation film (a silicon oxide film or the like) serving as an etching stopper is formed between the interlayered insulating film and the device isolation film and between the source-drain diffusion layer and the interlayered insulating film.
The above-mentioned method, as shown in
FIG. 23
, has an initial step of forming a MOS transistor having a source/drain diffusion layer
12
and a gate electrode
13
in a device region thereof surrounded by a device isolation film
11
(a silicon oxide film or the like) on a silicon substrate
16
.
Note that the MOS transistor has a structure that a gate oxide film
17
is disposed immediately below the gate electrode
13
. Moreover, silicon nitride films
18
and
19
are formed on the upper surface and side surfaces of the gate electrode
13
.
At this time, the surface of the source/drain diffusion layer
12
is exposed to the outside.
Then, an LPCVD method is employed to form a silicon nitride film
20
serving as an etching stopper is formed on the overall surface of the silicon substrate
16
. Then, the LPCVD method is again employed to form a interlayered insulating film (a silicon oxide film or the like)
14
on the silicon nitride film
20
.
Then, a RIE method is employed to etch the interlayered insulating film
14
as shown in
FIG. 24
so that a contact hole
10
is provided for the interlayered insulating film
14
. At this time, the silicon nitride film
20
has a high etching selection ratio with respect to the silicon oxide films for forming the device isolation film
11
and the interlayered insulating film
14
, the etching selection ratio being a ratio for the RIE process. Therefore, the silicon nitride film
20
is able to serve as the stopper. Thus, etching is stopped at a position on the upper surface of the silicon nitride film
20
. Therefore, the device isolation film
11
is not undesirably etched.
Then, only a portion of the silicon nitride film
20
existing in the bottom surface of the contact hole
10
is etched by, for example, an RIE method, as shown in FIG.
25
. As a result, the source/drain diffusion layer
12
is, in the bottom surface of the contact hole
10
, exposed to the outside.
Even if displacement in alignment of the mask causes the contact hole
10
and the device isolation film
11
to overlap as shown in
FIG. 25
, the silicon nitride film
20
is able to serve as a stopper because the silicon nitride film
20
has a high etching selection ratio in the RIE method with respect to the device isolation film (silicon oxide film or the like)
11
. Therefore, etching is stopped at a position on the surface of the device isolation film
11
. Thus, the device isolation film
11
is not undesirably etched.
As described above, the above-mentioned conventional method arranged to form the contact hole
10
for the source/drain diffusion layer
12
is structured in such a manner that the silicon nitride film
20
serving as the etching stopper is formed on the source/drain diffusion layer
12
and the device isolation film
11
. Therefore, the device isolation film
11
is not etched. Thus, enlargement of the leakage current can be prevented.
However, the above-mentioned method must perform the etching process two times when the contact hole is formed because the interlayered insulating film
14
and the silicon nitride film
20
must be etched individually.
Therefore, the above-mentioned method has a problem in that the manufacturing step increases and thus the manufacturing cost cannot be reduced as compared with another method arranged in such a manner that the silicon nitride film
20
serving as the etching stopper is not formed.
Another problem arises in that the structure in which the etching process is performed two times causes a stepped portion X to easily be generated in the interface between the interlayered insulating film
14
and the silicon nitride film
20
, as shown in FIG.
25
. Since the stepped portion X inhibits easy deposition of a material for the metal layer
15
when the metal layer
15
is formed in the contact hole
10
, there arises a problem in that the stepped portion X sometimes disconnects the metal layer
15
.
Another problem arises in that the not so large etching selection ratio between the silicon nitride film
20
and the substrate (silicon or silicide in the source-drain diffusion layer)
16
causes also the substrate
16
to be etched when the
Foley & Lardner
Gurley Lynne A.
Kabushiki Kaisha Toshiba
Niebling John F.
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