Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1999-09-20
2001-10-02
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S781000, C257S738000, C257S778000
Reexamination Certificate
active
06297562
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to semiconductive chips, and, more particularly, to bond pads of semiconductive chips.
BACKGROUND OF THE INVENTION
Conventional semiconductive chips include many active devices, i.e., transistors and diodes, as well as inactive devices, i.e., resistors and capacitors. These semiconductive chips include a plurality of bond pads, which are metallized areas on the periphery of the semiconductive chip for making a connection to a package pin. A small diameter gold or aluminum wire is bonded each of to the bond pads by application of heat and ultrasonic energy. Each of these bond wires electrically connects the semiconductive chip with a circuit or component of a substrate. In an effort to decrease the space occupied by semiconductive chips and the assembly steps associated with such semiconductive chips, flip chip solutions have become more prominent because they do not require wire bonding.
A conventional flip chip is essentially a semiconductive die with all terminations on one side of the chip in the form of solder bond pads or bump contacts. The surface of the flip chip having the bond pads is flipped over for attaching to a matching substrate in which interconnecting thin films and possibly also thin film components have previously been deposited. All electrical connections between the flip chip and the substrate are made simultaneously by applying heat or a combination of ultrasonic energy and pressure. With such conventional flip chips, the bond pads are not located on the active devices of the chip. Rather, the bond pads are intentionally located away from the active devices. See, for example, Column 4, lines 53-57 of U.S. Pat. No. 5,764,486. The bond pads are located away from the active devices because fabrication of the bond pads or attachment of contact studs to such bond pads may damage the active device if the active device is located underneath the bond pad. For example, the bonding of a contact stud (a rigid electrical conductor) to the bond pad of the flip chip may crack a transistor if the bond pad is located on the transistor, rendering the chip inoperable or significantly decreasing its reliability.
Despite the known drawbacks of locating bond pads on active devices of chips, attempts have been made to locate specially configured bond pads directly over some transistors. For example, one conventional flip chip includes a specifically configured gold bump located on a transistor cell of a chip. The gold bump is formed by depositing a 20-50 micron layer of gold on top of the transistor cell with an electroplating process. The gold bumps can then be bonded, such as soldered, to a matching substrate. However, fabrication of these gold bumps problematically requires several manufacturing steps, further complicating the construction of the flip chip.
SUMMARY OF THE INVENTION
Generally speaking, one object of the embodiments of the invention is to provide a semiconductive chip having a bond pad located on an active device of the chip, where the bond pad is configured such that a conductive stud can be bonded to the bond pad without damaging the active device.
According to one aspect of the present invention, a semiconductive chip includes at least one active device, and at least one bond pad located on the active device. The bond pad has at least one deformable member. The deformable member is deformable when a conductive stud is bonded to the bond pad.
According to another aspect of the present invention, a semiconductive chip includes at least one active device, and at least one bond pad located on the active device. The bond pad has a patterned portion that is deformable when a conductive stud is bonded to the bond pad so as to prevent damage to the active device during the bonding of the conductive stud to the bond pad.
In accordance with a further aspect of the present invention, a method includes ultrasonically bonding a conductive stud to a bond pad of a semiconductive chip. The bond pad is located on an active device of the semiconductive chip.
Another aspect of the present invention pertains to a method of deforming a deformable member of a bond pad of a semiconductive chip when bonding a conductive stud to the bond pad of the semiconductive chip. The bond pad is located on an active device of the semiconductive chip.
A further aspect of the present invention pertains to a semiconductive chip having at least one active device and at least one bond pad located on the active device. A conductive stud is ultrasonically bonded to the bond pad.
Other objects, advantages and features associated with the present invention will become readily apparent to those skilled in the art from the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modification in various obvious aspects, all without departing from the invention. Accordingly, the drawings and the description are to be regarded as illustrative in nature, and not limitative.
REFERENCES:
patent: 5349239 (1994-09-01), Sato
patent: 5373185 (1994-12-01), Sato
patent: 5640052 (1997-06-01), Tsukamoto
patent: 5669545 (1997-09-01), Pham et al.
patent: 5686762 (1997-11-01), Langley
patent: 5734193 (1998-03-01), Bayraktaroglu et al.
patent: 5736790 (1998-04-01), Iyogi et al.
patent: 5831337 (1998-11-01), Sato
patent: 5869899 (1999-02-01), Arledge et al.
patent: 5904499 (1999-05-01), Pace
patent: 5914536 (1999-06-01), Shizuki et al.
patent: 5939739 (1999-08-01), O'Keefe
patent: 5959363 (1999-09-01), Yamada et al.
patent: 5962925 (1999-10-01), Eifuku et al.
patent: 5973930 (1999-10-01), Ikeda et al.
patent: 6002172 (1999-12-01), Desai et al.
patent: 6016013 (2000-01-01), Baba
patent: 0 825 646A2 (1998-02-01), None
patent: 60013848 (1986-04-01), None
patent: 06201090 (1996-08-01), None
H.Sato, M.Miyauchi, K.Sakuno, M.Akagi. M.Hasegawa, J.K. Twynam, K.Yamamura and T.Tomita, “Bump Heat Sink Technology—A Novel Assembly Technology Suitable For Power HBTs”, Published 1993, pp. 337-340.
Keiji Yamamura, Hisashi Atarashi, Noriko Kakimoto, Naoki Sakota, Hiroya Sata, Masato Miyauchi, Katsuyuki Naito and Takashi Nukii, “Flip-Chip Bonding Technology for GaAs-MMIC Power Devices”, Published 1993, pp. 433-438.
Yutaka Tsukada, Shogo Mizumoto and Yasushi Kodama, “Build-up Printed Circuit Board and Bare Chip Packaging”, Published Date Unknown, pp. 1-9.
Tuomo Jaakola, Jaakko Lenkkeri and Jouko Vähäkangas, “Flip-Chip Joining Utilizing Gold Bumps”, Published Oct. 9, 1997, pp. 1-9.
Panasonic, Panasert “Flip Chip Bonding System”, Published 1998, pp. 1-11.
Burns Doane Swecker & Mathis L.L.P.
Cruz Lourdes
Lee Eddie
Telefonaktieboalget LM Ericsson (publ)
LandOfFree
Semiconductive chip having a bond pad located on an active... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductive chip having a bond pad located on an active..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductive chip having a bond pad located on an active... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2600909