Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2001-09-25
2003-12-02
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S706000, C257S780000, C257S779000, C257S787000
Reexamination Certificate
active
06657296
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having a heat dissipating element so as to improve heat dissipating efficiency.
BACKGROUND OF INVENTION
A BGA (ball grid array) semiconductor package employs a large quantity of solder balls acting as I/O connections in the interest to incorporate a chip of high integration. However, much heat is generated in operation of such a high integration chip. Therefore, how to effectively dissipate the generated heat is definitely a problem to solve.
In order to solve the heat dissipation problem, U.S. Pat. No. 5,216,278 proposes a BGA semiconductor package, in which a plurality of thermal balls are implanted on a bottom side of a substrate, so as to allow heat generated by a chip mounted on a top side opposing the bottom side of the substrate to be transmitted to a printed circuit board (PCB) connected to the semiconductor package. Accordingly, heat dissipating efficiency can be improved in such a semiconductor package. However, as the thermal balls implanted on the substrate are limited in quantity according to area on the substrate available for thermal ball implantation, the improvement in the heat dissipating efficiency is thus restricted.
Therefore, U.S. Pat. No. 5,642,261 discloses a semiconductor package having a heat sink mounted on a substrate, wherein the heat sink has a larger heat dissipating area so as to help eliminate the restriction on the improvement in the heat dissipating efficiency in the U.S. Pat. No. 5,216,278. As shown in
FIG. 6
, in the semiconductor package, the substrate
10
is formed with an opening
100
penetrating the substrate
10
, and the heat sink
11
is disposed in the opening
100
in a manner as to come into contact with a chip
12
, for allowing heat generated by the chip
12
to be directly dissipated through the heat sink
11
to the atmosphere. However, the formation of the opening
100
in the substrate
10
increases the cost; whereas due to the significant difference in coefficient of thermal expansion between the substrate
10
and the heat sink
11
, thermal stress produced during a temperature cycle and a reliability test causes cracks at an interface between the substrate
10
and the heat sink
11
. This allows external moisture to penetrate into the internal of the semiconductor package through the cracks, and thus reliability of the semiconductor package is undesirably affected.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package, which allows heat generated by a chip to be directly dissipated through a heat sink to the atmosphere without forming an opening on a substrate for attaching the heat sink to the substrate, so that the increase in fabrication cost can be eliminated and the heat sink can provide sufficient heat dissipating area for effectively dissipating the heat generated by the chip.
In accordance with the foregoing and other objectives, the present invention proposes a semiconductor package, comprising: a substrate having a top side and an opposing bottom side, wherein on the top side there is predefined a die-attach region formed with a plurality of thermal vias therewithin, and on the bottom side there is formed a thermal pad connecting to the thermal vias at a position corresponding to the die-attach region; at least one chip mounted on the die-attach region of the substrate and electrically connected to the substrate; a plurality of conductive elements electrically connected to the bottom side of the substrate for electrically connecting the chip to an external device; and an encapsulant formed on the top side of the substrate for encapsulating the chip.
In order to allow the conductive elements to be electrically connected to the external device properly, the thermal pad has a thickness to be necessarily smaller than the height of the conductive elements. Moreover, the thermal pad is attached to the substrate in a manner that edge sides of the thermal pad are encapsulated by solder mask covering the bottom side of the substrate, and a surface of the thermal pad not encapsulated by the solder mask is exposed to the atmosphere.
REFERENCES:
patent: 3593064 (1971-07-01), Wagner
patent: 5216278 (1993-06-01), Lin et al.
patent: 5642261 (1997-06-01), Bond et al.
patent: 5856911 (1999-01-01), Riley
patent: 5942795 (1999-08-01), Hoang
patent: 6249053 (2001-06-01), Nakata et al.
patent: 6265772 (2001-07-01), Yoshida
patent: 6359341 (2002-03-01), Huang et al.
Ho Tzong-Da
Huang Chien-Ping
Corless Peter F.
Cuneo Kamand
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
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