Semi-synchronous dual port FIFO

Details Semi-synchronous dual port FIFO Semi-synchronous dual port FIFO

1995-02-13

1996-09-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Serial read/write

365233, 365236, G11C 700

Patent

active

055555241

ABSTRACT:
An FIFO is provided which has two synchronous ports that may operate asynchronously to one another. The FIFO design is unaffected by gate delays, and is therefore especially useful in an integrated circuit where gate delays may not be easily controlled (such as a standard cell or gate array design.) In the FIFO, a write counter controlled by a write clock outputs a write address and a read counter controlled by a read clock with a different frequency outputs a read address. Synchronization circuits are provided to synchronize the read address to the write clock and the write address to the read clock. The synchronized read and write addresses are used to generate full and empty indicators for the FIFO and an occupancy level for the FIFO.

REFERENCES:
patent: 5084841 (1992-01-01), Williams et al.
patent: 5365485 (1994-11-01), Ward et al.
patent: 5426756 (1995-06-01), Shyi et al.

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