Electronic digital logic circuitry – Threshold
Reexamination Certificate
1998-01-08
2001-07-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Threshold
C326S119000, C326S121000
Reexamination Certificate
active
06262593
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of electronic circuits, and more particularly to threshold logic circuits for arithmetic, logic, and signal processing.
BACKGROUND
Most previous logic systems, such as Boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. In traditional Boolean logic that uses a CMOS or TTL implementation, a low voltage level on a signal line means “logic false” or the number “zero.” A high voltage level on the same line means “logic true” or the number “one.” Thus a signal line may assume one of two values, either of which ostensibly has meaning.
Typically, a sequential logic circuit will respond to a grouped set of inputs to generate an output. While a set of input signals propagates through the sequential circuit, the sequential circuit output is unreliable for a period of time corresponding to worst-case propagation delays through the individual logic gates. In traditional clocked Boolean logic circuits, however, a binary signal might—or might not—be valid at any given moment. Outputs of combinational circuits have a period of uncertainty during which input signals propagate through gates. Designers accommodate such periods of instability by analyzing the worst-case propagation delays through such circuits and sampling the signal only at predetermined times when the output is expected to be stable, often by latching the output into a register. The sampling time is determined by an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
While these traditional synchronous circuits have become the dominant class of logic, a substantial amount of design analysis is necessary to avoid a variety of timing-related problems, such as worst-case propagation delay and race conditions. In addition, the proportion of power and wafer area (“real estate”) that must be devoted to clocking has become substantial, and in certain instances can be a limiting factor to the total amount of functionality that can be integrated onto a single chip.
SUMMARY
An object of the invention is to provide threshold gates for use in asynchronous circuits.
A further object of the invention is to provide threshold gates using a semi-dynamic transistor design.
A further object of the invention is to provide threshold gates using dynamic transistor design.
A further object of the invention is to provide threshold gates adapted for receiving inputs on signal lines grouped into mutually exclusive assertion groups.
A further object of the invention is to provide asynchronous circuits from interconnected threshold gates.
A further object of the invention is to provide gates capable of operating with NULL signal states that have no arithmetic or logic meaning.
A further object of the invention is to provide gates capable of operating with the NULL state assigned to a high or low voltage state.
A further object of the invention is to provide staged circuits, where the NULL state may be assigned different voltage states in different stages.
These and other objects are achieved by providing threshold gate designs. In the preferred embodiments, threshold gates have output signals which switch between two states: ASSERTED and NULL. The ASSERTED state is assigned an arithmetic or logic meaning. The NULL state has no arithmetic or logic meaning. The NULL state may be assigned as a voltage level near the voltage of a voltage reference, such as a power source, or a voltage level near ground. Gate designs may be semi-dynamic or dynamic.
Certain designs are especially adapted for processing signals grouped into mutually exclusive assertion groups. In a mutually exclusive assertion group, at most one signal line will be ASSERTED at time.
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Hinze Jason J.
Sobelman Gerald Edward
Steptoe & Johnson LLP
Theseus Logic Inc.
Tokar Michael
Tran Anh
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