Semi-conductor memory device

Details Semi-conductor memory device Semi-conductor memory device

2000-06-28

2001-07-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S189070, C365S193000, C365S189110

Reexamination Certificate

active

06269029

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semi-conductor memory device, particularly to a semi-conductor memory device which realized an operation of low power and high speed by transferring data in a low voltage width by way of a data bus line structure pipelined.
2. Description of the Related Art
Generally, a DRAM being used as a main memory of a computer and a graphic memory requires a high band width for an enhancement of a performance of a system, a circuit structure of a method that an internal operational frequency of a DRAM is increased or of a pipeline and prefetch method is used to satisfy this requirements.
However, as an internal operation speed of a DRAM has a limit because of an internal operational principle of a word line access and sensing, a method that a number of data are transferred and outputted simultaneously to an input, output interface circuit in advance by many data bus lines is applied and a required band width is realized.
Therefore, in a memory device requiring a high speed operation such as a synchronous DRAM, D.D.R. SDRAM, Rambus DRAM, said prefetch method is used in an internal circuit, data bus lines of the number of 128 bits or more than 128 bits may be used to satisfy a band width required in a logic circuit even in an embedded memory device having a DRAM device therein.
However, a data bus line structure of a prior semi-conductor memory device generally transfers one datum to two lines, is composed of a structure using a signal of CMOS level(at this time, a CMOS level indicates a ground electric potential(Vss) and an electric power potential(Vdd)), there was a problem that this data bus line structure is inappropriate to cope with a high speed operation of more than 150 MHz, a consumption of an electric power increases very rapidly in a case that many data bus lines are used.
FIG. 1
shows a data bus line structure of a prior semi-conductor memory device. Referring to
FIG. 1
, the structure of
FIG. 1
has a structure that two global data bus lines transfer one datum, this structure is composed of 2n global data bus lines for transferring n data between a bank
100
composed of numerous memory cells and an input, output interface circuit part
200
.
Also, the bank
100
and the input, output interface circuit part
200
comprise n driving means
10
for driving each global data bus line, a data receiving means
20
for receiving two data carried respectively on two global data bus lines driven by the driving means
10
and comparing them and discriminating the data values as much as the number of data.
However, as described above, though a prior semi-conductor memory device had an advantage that a strong operation characteristic to a common mode noise by a data bus line structure using two data bus lines every each data for transferring data, a prior semi-conductor memory device had a drawback that an internal area of a chip increases considerably.
Also, in a case of a global data bus line being used generally, as it is composed of very long metal lines and a capacitance of a line is large considerably, in the case that numerous CMOS level data are transferred simultaneously via a number of global data bus lines, there was a problem that a considerable electric power consumption generates, and that it is difficult to cope with a high speed operation of more than 150 MHz due to a long consumption time of pre-charging.
SUMMARY OF THE INVENTION
The present invention is invented to solve the problem, it is an object of the present invention to provide a semi-conductor memory device realizing a low power consumption and a high speed operation by using a single global data bus line every each data and clamping an amplitude of a voltage to a level of an electric power voltage and using it.
To accomplish said object, a semi-conductor memory device according to the present invention comprises :
global data bus lines and single data strobe lines and reference comparing voltage lines with the number being identical to the number of data being coupled between a bank and an input, output interface circuit part;
a clamping means connected every each line for fixing the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines to a regular level of an electric potential;
a first to a third driving means connected to every ends of both sides of the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines, for controlling a drive of each lines by a combination of an input, output enable signal and a data output strobe signal and each data signal;
a first receiving means connected to ends of both sides of the data strobe lines, for receiving a strobe signal carried on the data strobe lines and comparing it with a reference comparing voltage and thereby outputting the data strobe signal;
a second receiving means connected to respective ends of both sides of the numerous global data bus lines, for comparing each data signal with a reference comparing voltage signal and outputting each data value under a control of a data strobe signal being outputted from the first receiving means.
Also, a semi-conductor memory device according to the present invention further comprises multiple pre-charge means connected to the global data bus lines and the data strobe lines respectively for pre-charging a data bus line by the clamping means in a high speed.


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