Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1999-10-27
2003-04-15
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S020000, C710S107000, C712S032000
Reexamination Certificate
active
06549961
ABSTRACT:
TECHNICAL FIELD
The present invention relates to determining access to protected resources in a multiprocessor system.
BACKGROUND ART
Multiprocessor systems use two or more processors to increase task execution speed and throughput. Each processor typically has local resources, such as cache memory, to which only that processor has access. Shared resources, such as memory, I/O devices, and the like, may be accessed by more than one processor. A typical multiprocessor architecture uses one or more bridges to interconnect processors and shared resources. Each bridge is connected to two or more processors through a processor bus. Shared resources are connected to the bridge through one or more resource buses.
In a multiprocessor system, a conflict results if more than one processor attempts to access the same resource at the same time. Conflicts are typically resolved through the use of semaphores. Each shared resource is assigned a semaphore. Before accessing the shared resource protected by a semaphore, the processor first checks the semaphore. If the semaphore indicates that the protected resource is available, the processor is granted access and the access is indicated by updating the semaphore. If the semaphore indicates the protected resource is not available, the processor is denied access.
Semaphore-based access control may be implemented in many different manners. A common technique is to locate semaphores in a central location such as at one of the processors or at the protected resource. A processor wishing to access the protected resource would check the semaphore for the protected resource through a processor bus interconnecting the requesting processor and the semaphore. If the processor is denied access, the processor executes a polling loop until the semaphore indicates that the requested resource is available. This creates two problems. First, the processor continues to execute instructions while waiting, wasting processor CPU cycles and generating heat. Second, processor bus cycles are wasted while the requesting processor checks the semaphore status. This reduces the effective bus bandwidth, potentially reducing the throughput of other processors.
Another technique is to store the value of each semaphore locally at each processor. Processors no longer utilize bus cycles in polling. However, processors still waste CPU cycles polling, generating heat without accomplishing any useful task. Also, either processor bus cycles must be wasted to update local semaphore copies or special hardware within each processor and communication busing must be used. A further problem is synchronizing the local semaphore values in each processor.
What is needed is to control access to protected resources in a multiprocessor system without wasting processor bus cycles or CPU instruction cycles and without requiring significant additional hardware.
DISCLOSURE OF INVENTION
It is an object of the present invention to control access to protected resources in a multiprocessor system.
It is another object of the present invention to control access to protected resources without requiring excessive processor bus cycles.
It is yet another object of the present invention to control access to protected resources without wasting CPU execution cycles.
It is still another object of the present invention to control access to protected resources without requiring excessive additional hardware.
In carrying out the above objects and other objects and features of the present invention, a multiprocessor system is provided. The multiprocessor system includes at least one protected resource. A plurality of processors generate requests to access the protected resources. A bridge interconnects each processor and protected resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.
In an embodiment of the present invention, the bridge resumes execution of the halted processor when the semaphore corresponding to the requested resource indicates the requested resource is available.
In another embodiment of the present invention, the multiprocessor system further includes a processor bus interconnecting the processors and the bridge and a resource bus interconnecting the protected resources and the bridge.
In still another embodiment of the present invention, each resource accesses at least one of many resource buses. The multiprocessor system further includes a crossbar switch for routing access requests to the requested resource when the requested resource is available.
In yet another embodiment of the present invention, the bridge is a northbridge. The northbridge may include a crossbar switch.
A method of controlling access to protected resources in a multiprocessor system is also provided. A request is received from a processor to access a protected resource. The state of a semaphore corresponding to the protected resource is examined to indicate the availability of the protected resource. If the semaphore indicates that the resource is available, the requesting processor is granted access to the protected resource. If the semaphore indicates that the resource is unavailable, the requesting processor is halted.
In an embodiment, the method further includes receiving a resource release from a processor granted access to the protected resource. If a processor is halted waiting for the released resource, execution is resumed by the halted processor.
The above objects and other objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.
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Gaffin Jeffrey
Infineon Technologies North America Corporation
Mai Rijue
LandOfFree
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