Selfaligned source/drain FinFET process flow

Details Selfaligned source/drain FinFET process flow Selfaligned source/drain FinFET process flow

2005-08-23

2005-08-23

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S164000, C438S283000, C438S284000, C257S347000, C257S368000, C257S401000

Reexamination Certificate

active

06933183

ABSTRACT:
A selfaligned FinFET is fabricated by defining a set of fins in a semiconductor wafer, depositing gate material over the fins, defining a gate hardmask having a thickness sufficient to withstand later etching steps, etching the gates material outside the hardmask to form the gate, depositing a conformal layer of insulator over the gate and the fins, etching the insulator anistotropically until the insulator over the fins is removed down to the substrate, the hardmask having a thickness such that a portion of the hardmask remains over the gate and sidewalls remain on the gate, and forming source and drain areas in the exposed fins while the gate is protected by the hardmask material.

REFERENCES:
patent: 6252284 (2001-06-01), Muller et al.
patent: 6342410 (2002-01-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 2004/0036126 (2004-02-01), Chau et al.

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