Self-tuning of signal path delay in circuit employing...

Details Self-tuning of signal path delay in circuit employing... Self-tuning of signal path delay in circuit employing...

2011-01-25

2011-01-25

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189120, C365S207000

Reexamination Certificate

active

07876631

ABSTRACT:
Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

REFERENCES:
patent: 6031779 (2000-02-01), Takahashi
patent: 6034920 (2000-03-01), Sukegawa et al.
patent: 7542332 (2009-06-01), Kim
patent: 7542348 (2009-06-01), Kim
patent: 2006/0220721 (2006-10-01), Vig
patent: 2008/0056031 (2008-03-01), Takahashi
International Search Report-PCT/ US2010/067657, International Search Authority-European Patent Office May 31, 2010.
Written Opinion-PCT/ US2010/067657, International Search Authority-European Patent Office May 31, 2010.

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